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publication number s29gl-n_01 revision 09 issue date november 16, 2007 s29gl-n mirrorbit ? flash family s29gl-n mirrorbit ? flash family cover sheet s29gl064n, s29gl032n 64 megabit, 32 megabit 3.0-volt only page mode flash memory featuring 110 nm mirror bit process technology data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
publication number s29gl-n_01 revision 09 issue date november 16, 2007 distinctive characteristics architectural advantages ? single power supply operation ? manufactured on 110 nm mirrorbit process technology ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? programmed and locked at the factory or by the customer ? flexible sector architecture ? 64mb (uniform sector models): one hundred twenty-eight 32 kword (64 kb) sectors ? 64 mb (boot sector models): one hundred twenty-seven 32 kword (64 kb) sectors + eight 4kword (8kb) boot sectors ? 32 mb (uniform sector models): sixty-four 32kword (64 kb) sectors ? 32 mb (boot sector models): sixty-three 32kword (64 kb) sectors + eight 4kword (8kb) boot sectors ? enhanced versatilei/o ? control ? all input levels (address, control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ? 100,000 erase cycles typical per sector ? 20-year data retention typical performance characteristics ? high performance ? 90 ns access time ? 8-word/16-byte page read buffer ? 25 ns page read time ? 16-word/32-byte write buffer which reduces overall programming time for multiple-word updates ? low power consumption ? 25 ma typical active read current ? 50 ma typical erase/program current ? 10 a typical standby mode current ? package options ? 48-pin tsop ? 56-pin tsop ? 64-ball fortified bga ? 48-ball fine-pitch bga software & hardware features ? software features ? advanced sector protection: offers persistent sector protection and password sector protection ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? unlock bypass program command reduces overall multiple-word programming time ? hardware features ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings on uniform sector models ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion s29gl-n mirrorbit ? flash family s29gl064n, s29gl032n 64 megabit, 32 megabit 3.0 volt-only page mode flash memory featuring 110 nm mirror bit process technology data sheet
4 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet general description the s29gl-n family of devices ar e 3.0-volt single-power flash memory manufactured using 110 nm mirrorbit technology. the s29gl064n is a 64-mb device organized as 4,194,304 words or 8,388,608 bytes. the s29gl032n is a 32-mb device organized as 2,09 7,152 words or 4,194,304 bytes. depending on the model number, the devices have 16-bit wide data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the byt e# input. the devices can be prog rammed either in the host system or in standard eprom programmers. access times as fast as 90 ns are available. note that each access time has a specific operating voltage range (v cc ) as specified in the product selector guide and the ordering information?s29gl032n , and ordering information?s29gl064n . package offerings include 48-pin tsop, 56-pin tsop, 48-ball fine-pitch bga and 64-ball fortified bga, depending on model num ber. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0-volt power supply for both read and write fu nctions. in addition to a v cc input, a high-voltage accelerated program (acc) feature provides shorter programming times through increased current on the wp#/acc inpu t. this feature is intended to facilitate factory throughput during system production, but ma y also be used in t he field if desired. the device is entirely command set compatible with the jedec single-power-s upply flash standard . commands are written to the device using standard microp rocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. the advanced sector protection features several levels of sector protection, which can disable both the program and erase operations in certai n sectors. persistent sector protection is a method that replaces the previous 12-volt controlled protection method. password se ctor protection is a highly sophisticated protection method that requires a password before cha nges to certain sectors are permitted. device programming and erasure are initiated thr ough command sequences. once a program or erase operation begins, the host system need only po ll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the o peration is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program dat a instead of four. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both pr ogram and erase operations in any combination of sectors of memory. this c an be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/ program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then co mplete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or wh en addresses are stable for a specified period of time. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp#/acc pin or wp# pin, depending on model number. the protect ed sector is still protected even during accelerated programming. the secured silicon sector provides a 128-word/256-byte area for c ode or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. spansion mirrorbit flash technology co mbines years of flash memory m anufacturing experience to produce the highest levels of quality, reliabili ty and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is prog rammed using hot electron injection.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 5 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. ordering information?s29gl032n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. ordering information?s29gl064n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.1 word/byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2 requirements for reading array data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.3 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.4 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.5 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.6 reset#: hardware reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 8.7 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.9 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.10 advanced sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.11 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.12 persistent sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.13 persistent protection mode lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.14 password sector protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.15 password and password protection mode lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.16 64-bit password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17 persistent protection bit lock (ppb lock bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.18 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.19 write protect (wp/acc#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.20 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9. common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.3 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.4 enter/exit secured silicon sector command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.5 program suspend/program resume command sequence . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.7 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.8 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.9 command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.10 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.11 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.12 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.13 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.14 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.15 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.16 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.17 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.18 dq1: write-to-buffer abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 13. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.1 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16. erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 17. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.1 ts048?48-pin standard thin small outline package (t sop) . . . . . . . . . . . . . . . . . . . . . . 74 17.2 ts056?56-pin standard thin small outline package (t sop) . . . . . . . . . . . . . . . . . . . . . . 75 17.3 vbk048?ball fine-pitch ball grid array (bga) 8.15x 6.15 mm package . . . . . . . . . . . . . . 76 17.4 laa064?64-ball fortified ball gr id array (bga) 13 x 11 mm package . . . . . . . . . . . . . . . . 77 18. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 7 data sheet figures figure 3.1 48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3.2 56-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3.3 64-ball fortified bga (laa 064) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3.4 48-ball fine-pitch bga (vbk 048) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5.1 s29gl064n logic symbol (models 01, 02, v1, v2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5.2 s29gl064n logic symbol (models 03, 04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5.3 s29gl064n logic symbol (models 06, 07, v6, v7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5.4 s29gl032n logic symbol (models 01, 02, v1, v2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5.5 s29gl032n logic symbol (models 03, 04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10.1 write buffer programming operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 10.2 program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 10.3 program suspend/program resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 10.4 erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 10.5 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 10.6 toggle bit algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 11.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 11.2 maximum positive overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 figure 14.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 14.2 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 15.1 v cc power-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 15.2 read operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 15.3 page read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 15.4 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 15.5 program operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 15.6 accelerated program timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 15.7 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 15.8 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 15.9 toggle bit timings (during embedde d algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 15.10 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 15.11 alternate ce# controlled write (erase/program) o peration timings . . . . . . . . . . . . . . . . . . .72
8 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet tables table 6.1 s29gl032n ordering options (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 7.1 s29gl064n valid combinations (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 8.1 device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 8.2 s29gl032n (models 01, 02, v1, v2) sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 8.3 s29gl032n (model 03) top boot sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 8.4 s29gl032n (model 04) bottom boot sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 8.5 s29gl064n (models 01, 02, v1, v2) sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 8.6 s29gl064n (model 03) top boot sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 8.7 s29gl064n (model 04) bottom boot sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 8.8 s29gl064n (models 06, 07, v6, v7) sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 8.9 autoselect codes, (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8.10 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 8.11 sector protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 9.1 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 9.2 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 9.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 9.4 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 0 table 10.1 command definitions (x16 mode, byte# = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 10.2 sector protection commands (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 10.3 command definitions (x8 mode, byte# = v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 10.4 sector protection commands (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 10.5 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 13.1 dc characteristics, cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 14.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 15.1 read-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 15.2 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 15.3 erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 15.4 alternate ce# controlled erase and program operati ons . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 16.1 tsop pin and bga package capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 9 data sheet 1. product selector guide 2. block diagram note **a max gl064n = a21, gl032n = a20. part number s29gl064n s29gl032n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 90 90 v io = 1.65?3.6 v 110 110 max. access time (ns) 90 110 90 110 max. ce# access time (ns) 90 110 90 110 max. page access time (ns) 25 30 25 30 max. oe# access time (ns) 25 30 25 30 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc byte# ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0
10 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 3. connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop and bga). the package and/or data integrity may be compromised if the pack age body is exposed to temperatures above 150c for prolonged periods of time. figure 3.1 48-pin standard tsop figure 3.2 56-pin standard tsop 1 16 2 3 4 5 6 7 8 17 1 8 19 20 21 22 2 3 24 9 10 11 12 1 3 14 15 4 8 33 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 25 3 2 3 1 3 0 29 2 8 27 26 a15 a1 8 a14 a1 3 a12 a11 a10 a9 a 8 a19 a20 we# re s et# a21 wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a 3 a2 a15 a1 8 a14 a1 3 a12 a11 a10 a9 a 8 a21 a20 we# re s et# acc wp# a19 a1 a17 a7 a6 a5 a4 a 3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq1 3 dq9 dq1 dq 8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq 3 dq10 a16 dq2 v io v ss dq15/a-1 dq7 dq14 dq6 dq1 3 dq9 dq1 dq 8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq 3 dq10 s 29gl064n, s 29gl0 3 2n (model s 0 3 , 04 only) s 29gl064n (model s 06, 07, v6, v7 only) nc on s 29gl0 3 2n 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 nc nc a15 a14 a1 3 a12 a11 a10 a9 a 8 a19 a20 we# re s et# a21 wp#/acc ry/by# a1 8 a17 a7 a6 a5 56 55 54 5 3 52 51 50 49 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq1 3 dq5 dq12 dq4 v cc dq11 dq 3 dq10 dq2 dq9 dq1 dq 8 dq0 2 3 24 25 26 27 2 8 a4 a 3 a2 a1 nc nc 3 4 33 3 2 3 1 3 0 29 oe# v ss ce# a0 nc v io nc on s 29gl0 3 2n s 29gl064n, s 29gl0 3 2n (model s 01, 02, v1, v2 only)
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 11 data sheet figure 3.3 64-ball fortified bga (laa 064) a2 c2 d2 e2 f2 g2 h2 a 3 c 3 d 3 e 3 f 3 g 3 h 3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# a16 a15 a14 a12 a1 3 dq1 3 dq6 dq14 dq7 a11 a10 a 8 a9 v cc dq4 dq12 dq5 a19 a21 re s et# we# dq11 dq 3 dq10 dq2 a20 a1 8 wp#/acc ry/by# dq9 dq1 dq 8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a 3 a1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc nc a 8 c 8 b2 b 3 b4 b5 b6 b7 b1 b 8 d 8 e 8 f 8 g 8 h 8 nc nc nc v ss v io nc nc nc nc on s 29gl0 3 2n s 29gl064n, s 29gl0 3 2n (model s 01, 02, 0 3 , 04, v1, v2 only) top view, b a ll s f a cing down nc on 0 3 , 04 option s
12 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet figure 3.4 48-ball fine- pitch bga (vbk 048) a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a 3 b 3 c 3 d 3 e 3 f 3 g 3 h 3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a1 3 dq1 3 dq6 dq14 dq7 a11 a10 a 8 a9 v cc dq4 dq12 dq5 a19 a21 re s et# we# dq11 dq 3 dq10 dq2 a20 a1 8 wp#/acc ry/by# dq9 dq1 dq 8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a 3 nc on s 29gl0 3 2n s 29gl064n, s 29gl0 3 2n (model s 0 3 , 04 only) top view, b a ll s f a cing down
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 13 data sheet 4. pin descriptions pin description a21?a0 22 address inputs (s29gl064n) a20?a0 21 address inputs (s29gl032n) dq7?dq0 8 data inputs/outputs dq14?dq0 15 data inputs/outputs dq15/a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# chip enable input oe# output enable input we# write enable input wp#/acc hardware write protect input/programming acceleration input acc acceleration input wp# hardware write protect input reset# hardware reset pin input ry/by# ready/busy output byte# selects 8-bit or 16-bit mode v cc 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io output buffer power v ss device ground nc pin not connected internally
14 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 5. logic symbols figure 5.1 s29gl064n logic symbol (models 01, 02, v1, v2) figure 5.2 s29gl064n logic symbol (models 03, 04) figure 5.3 s29gl064n logic symbol (models 06, 07, v6, v7) figure 5.4 s29gl032n logic symbol (models 01, 02, v1, v2) figure 5.5 s29gl032n logic symbol (models 03, 04) 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte# 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc byte# 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# ry/by# wp# acc v io 21 16 or 8 dq15?dq0 (a-1) a20?a0 ce# oe# we# reset# ry/by# wp#/acc byte# v io 21 16 or 8 dq15?dq0 (a-1) a20?a0 ce# oe# we# reset# ry/by# wp#/acc byte#
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 15 data sheet 6. ordering information?s29gl032n s29gl032n standard products standard products are available in several packa ges and operating ranges. the order number (valid combination) is formed by a combination of the following: s29gl032n 90 t a i 01 0 packing type 0= tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number 01 = x8/x16, v cc = v io = 2.7 ? 3.6 v, uniform sector, wp#/acc = v il protects highest addressed sector 02 = x8/x16, v cc = v io = 2.7 ? 3.6 v, uniform sector, wp#/acc = v il protects lowest addressed sector 03 = x8/x16, v cc = 2.7 ? 3.6 v, top boot sector, wp#/acc = v il protects top two addressed sectors 04 = x8/x16, v cc = 2.7 ? 3.6 v, bottom boot sector, wp#/acc = v il protects bottom two addressed sectors v1 = x8/x16, v cc = 2.7 ? 3.6 v, v io = 1.65 - 3.6 v, uniform sector, wp#/acc = v il protects highest addressed sector v2 = x8/x16, v cc = 2.7 ? 3.6 v, v io = 1.65 - 3.6 v, uniform sector, wp#/acc = v il protects lowest addressed sector temperature range i = industrial (?40c to +85c) package material set a = standard (note 4) f = pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations (90 = 90 ns, 11 = 110 ns) device number/description s29gl032n 32 megabit page-mode flash memory manufactured using 110 nm mirrorbit ? process technology, 3.0 volt-only read, program, and erase table 6.1 s29gl032n ordering options (note 4) s29gl032n valid combinations package description (notes) device number speed option package, material, & temperature range model number packing type s29gl032n 90 tfi 01, 02 0,2,3 (note 1) ts056 (note 2) tsop 11 v1, v2 90 ffi 01, 02 laa064 (note 3) fortified bga 11 v1, v2 90 tfi 03, 04 ts048 (note 2) tsop bfi vbk048 (note 3) fine-pitch bga ffi laa064 (note 3) fortified bga notes 1. type 0 is standard. specify others as required: tsops can be packed in types 0 and 3; bgas can be packed in types 0, 2, or 3. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading s29 and packing type designator from ordering part number. 4. contact local sales for availability for leaded lead-frame parts. valid combinations valid combinations list configurations plann ed to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
16 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 7. ordering information?s29gl064n s29gl064n standard products standard products are available in several packa ges and operating ranges. the order number (valid combination) is formed by a combination of the following: 8. device bus operations this section describes the requiremen ts and use of the device bus operati ons, which are initiated through the internal command register. the command register itse lf does not occupy any add ressable memory location. the register is a latch used to store the commands, along with the addr ess and data information needed to s29gl064n 90 t a i 02 2 packing type 0 = tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number 01 = x8/x16, v cc = v io = 2.7 ? 3.6 v, uniform sector, wp#/acc = v il protects highest addressed sector 02 = x8/x16, v cc = v io = 2.7 ? 3.6 v, uniform sector, wp#/acc = v il protects lowest addressed sector 03 = x8/x16, v cc = 2.7 ? 3.6 v, top boot sector, wp#/acc = v il protects top two addressed sectors 04 = x8/x16, v cc = 2.7 ? 3.6 v, bottom boot sector, wp#/acc = v il protects bottom two addressed sectors 06 = x16, v cc = 2.7 ? 3.6 v, uniform sector, wp# = v il protects highest addressed sector 07 = x16, v cc = 2.7 ? 3.6 v, uniform sector, wp# = v il protects lowest addressed sector v1 = x8/x16, v cc = 2.7 ? 3.6 v, v io = 1.65 - 3.6 v, uniform sector, wp#/acc = v il protects highes t addressed sector v2 = x8/x16, v cc = 2.7 ? 3.6 v, v io = 1.65 - 3.6 v, uniform sector, wp#/acc = v il protects lowest addressed sector v6 = x16, v cc = 2.7 ? 3.6 v, v io = 1.65 - 3.6 v, uniform sector, wp# = v il protects highest addressed sector v7 = x16, v cc = 2.7 ? 3.6 v, v io = 1.65 - 3.6 v, uniform sector, wp# = v il protects lowest addressed sector temperature range i = industrial (?40c to +85c) package material set a = standard (note 4) f = pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations (90 = 90 ns, 11 = 110 ns) device number/description s29gl064n, 64 megabit page-mode flash memory manufactured using 110 nm mirrorbit ? process technology, 3.0 volt-only read, program, and erase table 7.1 s29gl064n valid combinations (note 4) s29gl064n valid combinations package description device number speed option package, material & temperature range model number packing type s29gl064n 90 tfi 03, 04, 06, 07 0, 2, 3 (note 1) ts048 (note 2) tsop 11 v6, v7 90 01, 02 ts056 (note 2) tsop 11 v1, v2 90 bfi 03, 04 vbk048 (note 3) fine-pitch bga 90 ffi 01, 02, 03, 04 laa064 (note 3) fortified bga 11 v1, v2 notes 1. type 0 is standard. specify others as required: tsops can be packed in types 0 and 3; bgas can be packed in types 0, 2, or 3. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading s29 and packing type designator from ordering part number. 4. contact local sales for availability for leaded lead-frame parts. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 17 data sheet execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 8.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend l = logic low = v il h = logic high = v ih v id = 11.5?12.5 v v hh = 11.5?12.5 v x = don?t care sa = sector address a in = address in d in = data in d out = data out notes 1. if wp# = v il , the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for bo ot sector devices). if wp# = vih, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method describ ed in write protect (wp#). all sectors are unprotected when shipped from the factory (the secured silicon sector may be factory protected depending on version ordered.) 2. d in or d out as required by command sequence, data polli ng, or sector protect algorithm (see figure 10.5 on page 56 ). 8.1 word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or wo rd configuration. if the byte# pin is set at logic 1 , the device is in word configuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0 , the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated , and the dq15 pin is used as an input for the lsb (a-1) address function. 8.2 requirements for reading array data to read array data from the outputs, the syst em must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output cont rol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory cont ent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the de vice remains enabled for read access until the command register contents are altered. see reading array data on page 41 for more information. refer to the ac read-only operations table for timing specifications and the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. table 8.1 device bus operations operation ce# oe# we# reset# wp# acc addresses dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read llhh xxa in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) lhlh (note 1) xa in (note 2) (note 2) accelerated program lhlh (note 1) v hh a in (note 2) (note 2) standby v cc 0.3v x x v cc 0.3v x h x high-z high-z high-z output disable l h h h x x x high-z high-z high-z reset x x x l x x x high-z high-z high-z
18 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 8.2.1 page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words/16 bytes. the appropriate page is selected by the higher address bits a(max)?a3. address bits a2?a0 in word mode (a2?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor fa lls within that page) is equivalent to t pac c . when ce# is deasserted and reasserted for a subseq uent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the read-page addresses constant and changing the intra-read page addresses. 8.3 writing commands/command sequences to write a command or command sequence (which in cludes programming data to the device and erasing sectors of memory), the syste m must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programm ing. once the device enters the unlock bypass mode, only two wr ite cycles are required to program a word, instead of four. the word program command sequence on page 42 contains details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multip le sectors, or the entire device. tables 8.2 ? 8.8 indicate the address space that each sector occupies. refer to the dc characteristics table for the active current specification fo r the write mode. the ac characteristics section contains ti ming specification tables and timing diagrams for write operations. 8.3.1 write buffer write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective progra mming time than the standard programming algorithms. 8.3.2 accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc or acc pi n, depending on model number. this f unction is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the aforementioned unlock bypass mode, temporarily unprotects any pr otected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system wo uld use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc or acc pin, depending on model number, returns the device to normal operation. note that the wp#/acc or acc pin must not be at v hh for operations other than accelerated pr ogramming, or device damage may result. wp# contains an internal pullup; when unconnected, wp# is at v ih . 8.3.3 autoselect functions if the system writes the autosele ct command sequence, th e device enters the auto select mode. the system can then read autoselect codes from the internal regist er (which is separate from the memory array) on dq7? dq0. standard read cycle timings apply in this mode. refer to autoselect mode on page 29 and autoselect command sequence on page 42 for more information.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 19 data sheet 8.4 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when t he ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device is in the standby mode, but the standby current is greater. the device requires standard access time (t ce ) for read access when the device is in eith er of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. refer to the dc characteristics on page 62 for the standby current specification. 8.5 automatic sleep mode the automatic sleep mode minimizes flash device ener gy consumption. the devi ce automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals . standard address access timings pr ovide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics on page 62 for the automatic sleep mode current specification. 8.6 reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, hi-z all output pins, and ignores all read/writ e commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the oper ation that was interrupted should be reinitiated once the device is ready to acc ept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current is greater. the reset# pin may be tied to the system reset circuitry. a system rese t would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. refer to the ac characteristics t ables for reset# parameters and to figure 15.4 on page 66 for the timing diagram. 8.7 output disable mode when the oe# input is at v ih , output from the device is disabled. th e output pins are placed in the high impedance state.
20 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet table 8.2 s29gl032n (models 01, 02, v1, v2) sector addresses sector a20-a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a20-a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000 64/32 000000h?00ffffh 000000h?007fffh sa32 100000 64/32 200000h?20ffffh 100000h?107fffh sa1 000001 64/32 010000h?01ffffh 008000h?00ffffh sa33 100001 64/32 210000h?21ffffh 108000h?10ffffh sa2 000010 64/32 020000h?02ffffh 010000h?017fffh sa34 100010 64/32 220000h?22ffffh 110000h?117fffh sa3 000011 64/32 030000h?03ffffh 018000h?01ffffh sa35 100011 64/32 230000h?23ffffh 118000h?11ffffh sa4 000100 64/32 040000h?04ffffh 020000h?027fffh sa36 100100 64/32 240000h?24ffffh 120000h?127fffh sa5 000101 64/32 050000h?05ffffh 028000h?02ffffh sa37 100101 64/32 250000h?25ffffh 128000h?12ffffh sa6 000110 64/32 060000h?06ffffh 030000h?037fffh sa38 100110 64/32 260000h?26ffffh 130000h?137fffh sa7 000111 64/32 070000h?07ffffh 038000h?03ffffh sa39 100111 64/32 270000h?27ffffh 138000h?13ffffh sa8 001000 64/32 080000h?08ffffh 040000h?047fffh sa40 101000 64/32 280000h?28ffffh 140000h?147fffh sa9 001001 64/32 090000h?09ffffh 048000h?04ffffh sa41 101001 64/32 290000h?29ffffh 148000h?14ffffh sa10 001010 64/32 0a0000h?0affffh 050000h?057fffh sa42 101010 64/32 2a0000h?2affffh 150000h?157fffh sa11 001011 64/32 0b0000h?0bffffh 058000h?05ffffh sa43 101011 64/32 2b0000h?2bffffh 158000h?15ffffh sa12 001100 64/32 0c0000h?0cffffh 060000h?067fffh sa44 101100 64/32 2c0000h?2cffffh 160000h?167fffh sa13 001101 64/32 0d0000h?0dffffh 068000h?06ffffh sa45 101101 64/32 2d0000h?2dffffh 168000h?16ffffh sa14 001110 64/32 0e0000h?0effffh 070000h?077fffh sa46 101110 64/32 2e0000h?2effffh 170000h?177fffh sa15 001111 64/32 0f0000h?0fffffh 078000h?07ffffh sa47 101111 64/32 2f0000h?2fffffh 178000h?17ffffh sa16 010000 64/32 100000h?10ffffh 080000h?087fffh sa48 110000 64/32 300000h?30ffffh 180000h?187fffh sa17 010001 64/32 110000h?11ffffh 088000h?08ffffh sa49 110001 64/32 310000h?31ffffh 188000h?18ffffh sa18 010010 64/32 120000h?12ffffh 090000h?097fffh sa50 110010 64/32 320000h?32ffffh 190000h?197fffh sa19 010011 64/32 130000h?13ffffh 098000h?09ffffh sa51 110011 64/32 330000h?33ffffh 198000h?19ffffh sa20 010100 64/32 140000h?14ffffh 0a0000h?0a7fffh sa52 110100 64/32 340000h?34ffffh 1a0000h?1a7fffh sa21 010101 64/32 150000h?15ffffh 0a8000h?0affffh sa53 110101 64/32 350000h?35ffffh 1a8000h?1affffh sa22 010110 64/32 160000h?16ffffh 0b0000h?0b7fffh sa54 110110 64/32 360000h?36ffffh 1b0000h?1b7fffh sa23 010111 64/32 170000h?17ffffh 0b8000h?0bffffh sa55 110111 64/32 370000h?37ffffh 1b8000h?1bffffh sa24 011000 64/32 180000h?18ffffh 0c0000h?0c7fffh sa56 111000 64/32 380000h?38ffffh 1c0000h?1c7fffh sa25 011001 64/32 190000h?19ffffh 0c8000h?0cffffh sa57 111001 64/32 390000h?39ffffh 1c8000h?1cffffh sa26 011010 64/32 1a0000h?1affffh 0d0000h?0d7fffh sa58 111010 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa27 011011 64/32 1b0000h?1bffffh 0d8000h?0dffffh sa59 111011 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa28 011100 64/32 1c0000h?1cffffh 0e0000h?0e7fffh sa60 111100 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa29 011101 64/32 1d0000h?1dffffh 0e8000h?0effffh sa61 111101 64/32 3d0000h?3dffffh 1e8000h?1effffh sa30 011110 64/32 1e0000h?1effffh 0f0000h?0f7fffh sa62 111110 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa31 011111 64/32 1f0000h?1fffffh 0f8000h?0fffffh sa63 111111 64/32 3f0000h?3fffffh 1f8000h?1fffffh
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 21 data sheet table 8.3 s29gl032n (model 03) top boot sector addresses sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa36 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa1 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa37 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa2 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa38 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa3 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa39 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa4 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa40 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa5 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa41 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa6 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa42 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa7 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa43 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa8 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa44 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa9 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa45 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa10 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa46 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa11 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa47 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa12 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa48 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa13 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa49 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa14 001110xxx 64/32 0e0000h?0effffh 70000h?77fffh sa50 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa15 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa51 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa16 010000xxx 64/32 100000h?10ffffh 80000h?87fffh sa52 100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa17 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa53 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa18 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa54 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa19 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa55 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa20 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa56 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa21 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa57 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa22 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa58 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa23 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa59 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa24 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa60 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa25 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa61 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa26 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa62 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa27 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa63 111111000 8/4 3f0000h?3f1fffh 1f8000h?1f8fffh sa28 011100xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa64 111111001 8/4 3f2000h?3f3fffh 1f9000h?1f9fffh sa29 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa65 111111010 8/4 3f4000h?3f5fffh 1fa000h?1fafffh sa30 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa66 111111011 8/4 3f6000h?3f7fffh 1fb000h?1fbfffh sa31 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa67 111111100 8/4 3f8000h?3f9fffh 1fc000h?1fcfffh sa32 100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa68 111111101 8/4 3fa000h?3fbfffh 1fd000h?1fdfffh sa33 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa69 111111110 8/4 3fc000h?3fdfffh 1fe000h?1fefffh sa34 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa70 111111111 8/4 3fe000h?3fffffh 1ff000h?1fffffh sa35 100011xxx 64/32 230000h?23ffffh 118000h?11ffffh
22 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet table 8.4 s29gl032n (model 04) bottom boot sector addresses sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a20?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 000000000 8/4 000000h?001fffh 00000h?00fffh sa35 011100xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa1 000000001 8/4 002000h?003fffh 01000h?01fffh sa36 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa2 000000010 8/4 004000h?005fffh 02000h?02fffh sa37 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa3 000000011 8/4 006000h?007fffh 03000h?03fffh sa38 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa4 000000100 8/4 008000h?009fffh 04000h?04fffh sa39 100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa5 000000101 8/4 00a000h?00bfffh 05000h?05fffh sa40 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa6 000000110 8/4 00c000h?00dfffh 06000h?06fffh sa41 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa7 000000111 8/4 00e000h?00ffffh 07000h?07fffh sa42 100011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa8 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa43 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa9 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa44 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa10 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa45 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa11 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa46 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa12 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa47 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa13 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa48 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa14 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa49 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa15 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa50 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa16 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa51 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa17 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa52 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa18 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa53 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa19 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa54 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa20 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa55 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa21 001110xxx 64/32 0e0000h?0effffh 70000h?77fffh sa56 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa22 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa57 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa23 010000xxx 64/32 100000h?10ffffh 80000h?87fffh sa58 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa24 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa59 110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa25 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa60 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa26 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa61 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa27 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa62 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa28 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa63 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa29 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa64 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa30 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa65 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa31 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa66 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa32 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa67 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa33 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa68 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa34 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa69 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa70 111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 23 data sheet table 8.5 s29gl064n (models 01, 02, v1, v2) sector addresses (sheet 1 of 2) sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 0000000 64/32 000000h?00ffffh 000000h?007fffh sa64 1000000 64/32 400000h?40ffffh 200000h?207fffh sa1 0000001 64/32 010000h?01ffffh 008000h?00ffffh sa65 1000001 64/32 410000h?41ffffh 208000h?20ffffh sa2 0000010 64/32 020000h?02ffffh 010000h?017fffh sa66 1000010 64/32 420000h?42ffffh 210000h?217fffh sa3 0000011 64/32 030000h?03ffffh 018000h?01ffffh sa67 1000011 64/32 430000h?43ffffh 218000h?21ffffh sa4 0000100 64/32 040000h?04ffffh 020000h?027fffh sa68 1000100 64/32 440000h?44ffffh 220000h?227fffh sa5 0000101 64/32 050000h?05ffffh 028000h?02ffffh sa69 1000101 64/32 450000h?45ffffh 228000h?22ffffh sa6 0000110 64/32 060000h?06ffffh 030000h?037fffh sa70 1000110 64/32 460000h?46ffffh 230000h?237fffh sa7 0000111 64/32 070000h?07ffffh 038000h?03ffffh sa71 1000111 64/32 470000h?47ffffh 238000h?23ffffh sa8 0001000 64/32 080000h?08ffffh 040000h?047fffh sa72 1001000 64/32 480000h?48ffffh 240000h?247fffh sa9 0001001 64/32 090000h?09ffffh 048000h?04ffffh sa73 1001001 64/32 490000h?49ffffh 248000h?24ffffh sa10 0001010 64/32 0a0000h?0affffh 050000h?057fffh sa74 1001010 64/32 4a0000h?4affffh 250000h?257fffh sa11 0001011 64/32 0b0000h?0bffffh 058000h?05ffffh sa75 1001011 64/32 4b0000h?4bffffh 258000h?25ffffh sa12 0001100 64/32 0c0000h?0cffffh 060000h?067fffh sa76 1001100 64/32 4c0000h?4cffffh 260000h?267fffh sa13 0001101 64/32 0d0000h?0dffffh 068000h?06ffffh sa77 1001101 64/32 4d0000h?4dffffh 268000h?26ffffh sa14 0001110 64/32 0e0000h?0effffh 070000h?077fffh sa78 1001110 64/32 4e0000h?4effffh 270000h?277fffh sa15 0001111 64/32 0f0000h?0fffffh 078000h?07ffffh sa79 1001111 64/32 4f0000h?4fffffh 278000h?27ffffh sa16 0010000 64/32 100000h?10ffffh 080000h?087fffh sa80 1010000 64/32 500000h?50ffffh 280000h?287fffh sa17 0010001 64/32 110000h?11ffffh 088000h?08ffffh sa81 1010001 64/32 510000h?51ffffh 288000h?28ffffh sa18 0010010 64/32 120000h?12ffffh 090000h?097fffh sa82 1010010 64/32 520000h?52ffffh 290000h?297fffh sa19 0010011 64/32 130000h?13ffffh 098000h?09ffffh sa83 1010011 64/32 530000h?53ffffh 298000h?29ffffh sa20 0010100 64/32 140000h?14ffffh 0a0000h?0a7fffh sa84 1010100 64/32 540000h?54ffffh 2a0000h?2a7fffh sa21 0010101 64/32 150000h?15ffffh 0a8000h?0affffh sa85 1010101 64/32 550000h?55ffffh 2a8000h?2affffh sa22 0010110 64/32 160000h?16ffffh 0b0000h?0b7fffh sa86 1010110 64/32 560000h?56ffffh 2b0000h?2b7fffh sa23 0010111 64/32 170000h?17ffffh 0b8000h?0bffffh sa87 1010111 64/32 570000h?57ffffh 2b8000h?2bffffh sa24 0011000 64/32 180000h?18ffffh 0c0000h?0c7fffh sa88 1011000 64/32 580000h?58ffffh 2c0000h?2c7fffh sa25 0011001 64/32 190000h?19ffffh 0c8000h?0cffffh sa89 1011001 64/32 590000h?59ffffh 2c8000h?2cffffh sa26 0011010 64/32 1a0000h?1affffh 0d0000h?0d7fffh sa90 1011010 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa27 0011011 64/32 1b0000h?1bffffh 0d8000h?0dffffh sa91 1011011 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa28 0011100 64/32 1c0000h?1cffffh 0e0000h?0e7fffh sa92 1011100 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa29 0011101 64/32 1d0000h?1dffffh 0e8000h?0effffh sa93 1011101 64/32 5d0000h?5dffffh 2e8000h?2effffh sa30 0011110 64/32 1e0000h?1effffh 0f0000h?0f7fffh sa94 1011110 64/32 5e0000h?5effffh 2f0000h?2f7fffh sa31 0011111 64/32 1f0000h?1fffffh 0f8000h?0fffffh sa95 1011111 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa32 0100000 64/32 200000h?20ffffh 100000h?107fffh sa96 1100000 64/32 600000h?60ffffh 300000h?307fffh sa33 0100001 64/32 210000h?21ffffh 108000h?10ffffh sa97 1100001 64/32 610000h?61ffffh 308000h?30ffffh sa34 0100010 64/32 220000h?22ffffh 110000h?117fffh sa98 1100010 64/32 620000h?62ffffh 310000h?317fffh sa35 0100011 64/32 230000h?23ffffh 118000h?11ffffh sa99 1100011 64/32 630000h?63ffffh 318000h?31ffffh sa36 0100100 64/32 240000h?24ffffh 120000h?127fffh sa100 1100100 64/32 640000h?64ffffh 320000h?327fffh sa37 0100101 64/32 250000h?25ffffh 128000h?12ffffh sa101 1100101 64/32 650000h?65ffffh 328000h?32ffffh sa38 0100110 64/32 260000h?26ffffh 130000h?137fffh sa102 1100110 64/32 660000h?66ffffh 330000h?337fffh sa39 0100111 64/32 270000h?27ffffh 138000h?13ffffh sa103 1100111 64/32 670000h?67ffffh 338000h?33ffffh sa40 0101000 64/32 280000h?28ffffh 140000h?147fffh sa104 1101000 64/32 680000h?68ffffh 340000h?347fffh sa41 0101001 64/32 290000h?29ffffh 148000h?14ffffh sa105 1101001 64/32 690000h?69ffffh 348000h?34ffffh sa42 0101010 64/32 2a0000h?2affffh 150000h?157fffh sa106 1101010 64/32 6a0000h?6affffh 350000h?357fffh sa43 0101011 64/32 2b0000h?2bffffh 158000h?15ffffh sa107 1101011 64/32 6b0000h?6bffffh 358000h?35ffffh sa44 0101100 64/32 2c0000h?2cffffh 160000h?167fffh sa108 1101100 64/32 6c0000h?6cffffh 360000h?367fffh sa45 0101101 64/32 2d0000h?2dffffh 168000h?16ffffh sa109 1101101 64/32 6d0000h?6dffffh 368000h?36ffffh
24 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet sa46 0101110 64/32 2e0000h?2effffh 170000h?177fffh sa110 1101110 64/32 6e0000h?6effffh 370000h?377fffh sa47 0101111 64/32 2f0000h?2fffffh 178000h?17ffffh sa111 1101111 64/32 6f0000h?6fffffh 378000h?37ffffh sa48 0110000 64/32 300000h?30ffffh 180000h?187fffh sa112 1110000 64/32 700000h?70ffffh 380000h?387fffh sa49 0110001 64/32 310000h?31ffffh 188000h?18ffffh sa113 1110001 64/32 710000h?71ffffh 388000h?38ffffh sa50 0110010 64/32 320000h?32ffffh 190000h?197fffh sa114 1110010 64/32 720000h?72ffffh 390000h?397fffh sa51 0110011 64/32 330000h?33ffffh 198000h?19ffffh sa115 1110011 64/32 730000h?73ffffh 398000h?39ffffh sa52 0110100 64/32 340000h?34ffffh 1a0000h?1a7fffh sa116 1110100 64/32 740000h?74ffffh 3a0000h?3a7fffh sa53 0110101 64/32 350000h?35ffffh 1a8000h?1affffh sa117 1110101 64/32 750000h?75ffffh 3a8000h?3affffh sa54 0110110 64/32 360000h?36ffffh 1b0000h?1b7fffh sa118 1110110 64/32 760000h?76ffffh 3b0000h?3b7fffh sa55 0110111 64/32 370000h?37ffffh 1b8000h?1bffffh sa119 1110111 64/32 770000h?77ffffh 3b8000h?3bffffh sa56 0111000 64/32 380000h?38ffffh 1c0000h?1c7fffh sa120 1111000 64/32 780000h?78ffffh 3c0000h?3c7fffh sa57 0111001 64/32 390000h?39ffffh 1c8000h?1cffffh sa121 1111001 64/32 790000h?79ffffh 3c8000h?3cffffh sa58 0111010 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa122 1111010 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa59 0111011 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa123 1111011 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa60 0111100 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa124 1111100 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa61 0111101 64/32 3d0000h?3dffffh 1e8000h?1effffh sa125 1111101 64/32 7d0000h?7dffffh 3e8000h?3effffh sa62 0111110 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa126 1111110 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa63 0111111 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa127 1111111 64/32 7f0000h?7fffffh 3f8000h?3fffffh table 8.6 s29gl064n (model 03) top boot se ctor addresses (sheet 1 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 0000000xxx 64/32 000000h?00ffffh 000000h?007fffh sa68 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa1 0000001xxx 64/32 010000h?01ffffh 008000h?00ffffh sa69 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa2 0000010xxx 64/32 020000h?02ffffh 010000h?017fffh sa70 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa3 0000011xxx 64/32 030000h?03ffffh 018000h?01ffffh sa71 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa4 0000100xxx 64/32 040000h?04ffffh 020000h?027fffh sa72 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa5 0000101xxx 64/32 050000h?05ffffh 028000h?02ffffh sa73 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa6 0000110xxx 64/32 060000h?06ffffh 030000h?037fffh sa74 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa7 0000111xxx 64/32 070000h?07ffffh 038000h?03ffffh sa75 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa8 0001000xxx 64/32 080000h?08ffffh 040000h?047fffh sa76 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa9 0001001xxx 64/32 090000h?09ffffh 048000h?04ffffh sa77 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa10 0001010xxx 64/32 0a0000h?0affffh 050000h?057fffh sa78 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa11 0001011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh sa79 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa12 0001100xxx 64/32 0c0000h?0cffffh 060000h?067fffh sa80 1010000xxx 64/32 500000h?50ffffh 280000h?287fffh sa13 0001101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh sa81 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa14 0001110xxx 64/32 0e0000h?0effffh 070000h?077fffh sa82 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa15 0001111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh sa83 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa16 0010000xxx 64/32 100000h?10ffffh 080000h?087fffh sa84 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa17 0010001xxx 64/32 110000h?11ffffh 088000h?08ffffh sa85 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa18 0010010xxx 64/32 120000h?12ffffh 090000h?097fffh sa86 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa19 0010011xxx 64/32 130000h?13ffffh 098000h?09ffffh sa87 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa20 0010100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh sa88 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa21 0010101xxx 64/32 150000h?15ffffh 0a8000h?0affffh sa89 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa22 0010110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh sa90 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh table 8.5 s29gl064n (models 01, 02, v1, v2) sector addresses (sheet 2 of 2) sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a15 sector size (kb/ kwords) 8-bit address range 16-bit address range
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 25 data sheet sa23 0010111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh sa91 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa24 0011000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh sa92 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa25 0011001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh sa93 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa26 0011010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh sa94 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2f7fffh sa27 0011011xxx 64/32 1b0000h?1bffffh 0d8000h?0dffffh sa95 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa28 0011100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh sa96 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa29 0011101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh sa97 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa30 0011110xxx 64/32 1e0000h?1effffh 0f0000h?0f7fffh sa98 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa31 0011111xxx 64/32 1f0000h?1fffffh 0f8000h?0fffffh sa99 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa32 0100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa100 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa33 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa101 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa34 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa102 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa35 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa103 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa36 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa104 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa37 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa105 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa38 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa106 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa39 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa107 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa40 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa108 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa41 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa109 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa42 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa110 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa43 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa111 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa44 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa112 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa45 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa113 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa46 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa114 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa47 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa115 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa48 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa116 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa49 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa117 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa50 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa118 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa51 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa119 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa52 0110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa120 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa53 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa121 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa54 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa122 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa55 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa123 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa56 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa124 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa57 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa125 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa58 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa126 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa59 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dff ffh sa127 1111111000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh sa60 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa128 1111111001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh sa61 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa 129 1111111010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh sa62 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7ff fh sa130 1111111011 8/4 7f6000h?7f7fffh 3fb000h?3fbfffh sa63 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa131 1111111100 8/4 7f8000h?7f9fffh 3fc000h?3fcfffh sa64 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa 132 1111111101 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh sa65 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh s a133 1111111110 8/4 7fc000h?7fdfffh 3fe000h?3fefffh sa66 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa134 1111111111 8/4 7fe000h?7fffffh 3ff000h?3fffffh sa67 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh table 8.6 s29gl064n (model 03) top boot se ctor addresses (sheet 2 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range
26 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet table 8.7 s29gl064n (model 04) bottom boot sector addresses (sheet 1 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sa0 0000000000 8/4 000000h?001fffh 000000h?000fffh sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa1 0000000001 8/4 002000h?003fffh 001000h?001fffh sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa2 0000000010 8/4 004000h?005fffh 002000h?002fffh sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa3 0000000011 8/4 006000h?007fffh 003000h?003fffh sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa4 0000000100 8/4 008000h?009fffh 004000h?004fffh sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa5 0000000101 8/4 00a000h?00bfffh 005000h?005fffh sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa6 0000000110 8/4 00c000h?00dfffh 006000h?006fffh sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa7 0000000111 8/4 00e000h?00ffffh 007000h?007fffh sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa8 0000001xxx 64/32 010000h?01ffffh 008000h?00ffffh sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa9 0000010xxx 64/32 020000h?02ffffh 010000h?017fffh sa54 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa10 0000011xxx 64/32 030000h?03ffffh 018000h?01ffffh sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa11 0000100xxx 64/32 040000h?04ffffh 020000h?027fffh sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa12 0000101xxx 64/32 050000h?05ffffh 028000h?02ffffh sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa13 0000110xxx 64/32 060000h?06ffffh 030000h?037fffh sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa14 0000111xxx 64/32 070000h?07ffffh 038000h?03ffffh sa59 0110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa15 0001000xxx 64/32 080000h?08ffffh 040000h?047fffh sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa16 0001001xxx 64/32 090000h?09ffffh 048000h?04ffffh sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa17 0001010xxx 64/32 0a0000h?0affffh 050000h?057fffh sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa18 0001011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa19 0001100xxx 64/32 0c0000h?0cffffh 060000h?067fffh sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa20 0001101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa21 0001110xxx 64/32 0e0000h?0effffh 070000h?077fffh sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa22 0001111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa23 0010000xxx 64/32 100000h?10ffffh 080000h?087fffh sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa24 0010001xxx 64/32 110000h?11ffffh 088000h?08ffffh sa69 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa25 0010010xxx 64/32 120000h?12ffffh 090000h?097fffh sa70 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa26 0010011xxx 64/32 130000h?13ffffh 098000h?09ffffh sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa27 0010100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh sa72 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa28 0010101xxx 64/32 150000h?15ffffh 0a8000h?0affffh sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa29 0010110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa30 0010111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa31 0011000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh sa76 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa32 0011001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa33 0011010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa34 0011011xxx 64/32 1b0000h?1bffffh 0d8000h?0dffffh sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa35 0011100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa36 0011101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa37 0011110xxx 64/32 1e0000h?1effffh 0f0000h?0f7fffh sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa38 0011111xxx 64/32 1f0000h?1fffffh 0f8000h?0fffffh sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa39 0100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa40 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa86 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa42 0100011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 27 data sheet sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2f7fffh sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa124 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa129 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa131 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa132 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa133 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa134 1111111xxx 64/32 7f0000h?7fffffh 3f8000h?3fffffh table 8.8 s29gl064n (models 06, 07, v6, v7) sector addresses (sheet 1 of 2) sector a21?a15 16-bit address range sector a21?a15 16-bit address range sa0 0000000 000000?007fff sa64 1000000 100000?107fff sa1 0000001 008000?00ffff sa65 1000001 108000?10ffff sa2 0000010 010000?017fff sa66 1000010 110000?117fff sa3 0000011 018000?01ffff sa67 1000011 118000?11ffff sa4 0000100 020000?027fff sa68 1000100 120000?127fff sa5 0000101 028000?02ffff sa69 1000101 128000?12ffff sa6 0000110 030000?037fff sa70 1000110 130000?137fff sa7 0000111 038000?03ffff sa71 1000111 138000?13ffff sa8 0001000 040000?047fff sa72 1001000 140000?147fff sa9 0001001 048000?04ffff sa73 1001001 148000?14ffff sa10 0001010 050000?057fff sa74 1001010 150000?157fff sa11 0001011 058000?05ffff sa75 1001011 158000?15ffff sa12 0001100 060000?067fff sa76 1001100 160000?167fff sa13 0001101 068000?06ffff sa77 1001101 168000?16ffff sa14 0001110 070000?077fff sa78 1001110 170000?177fff sa15 0001111 078000?07ffff sa79 1001111 178000?17ffff sa16 0010000 080000?087fff sa80 1010000 180000?187fff sa17 0010001 088000?08ffff sa81 1010001 188000?18ffff sa18 0010010 090000?097fff sa82 1010010 190000?197fff table 8.7 s29gl064n (model 04) bottom boot sector addresses (sheet 2 of 2) sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range sector a21?a12 sector size (kb/ kwords) 8-bit address range 16-bit address range
28 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet sa19 0010011 098000?09ffff sa83 1010011 198000?19ffff sa20 0010100 0a0000?0a7fff sa84 1010100 1a0000?1a7fff sa21 0010101 0a8000?0affff sa85 1010101 1a8000?1affff sa22 0010110 0b0000?0b7fff sa86 1010110 1b0000?1b7fff sa23 0010111 0b8000?0bffff sa87 1010111 1b8000?1bffff sa24 0011000 0c0000?0c7fff sa88 1011000 1c0000?1c7fff sa25 0011001 0c8000?0cffff sa89 1011001 1c8000?1cffff sa26 0011010 0d0000?0d7fff sa90 1011010 1d0000?1d7fff sa27 0011011 0d8000?0dffff sa91 1011011 1d8000?1dffff sa28 0011100 0e0000?0e7fff sa92 1011100 1e0000?1e7fff sa29 0011101 0e8000?0effff sa93 1011101 1e8000?1effff sa30 0011110 0f0000?0f7fff sa94 1011110 1f0000?1f7fff sa31 0011111 0f8000?0fffff sa95 1011111 1f8000?1fffff sa32 0100000 200000?207fff sa96 1100000 300000?307fff sa33 0100001 208000?20ffff sa97 1100001 308000?30ffff sa34 0100010 210000?217fff sa98 1100010 310000?317fff sa35 0100011 218000?21ffff sa99 1100011 318000?31ffff sa36 0100100 220000?227fff sa100 1100100 320000?327fff sa37 0100101 228000?22ffff sa101 1100101 328000?32ffff sa38 0100110 230000?237fff sa102 1100110 330000?337fff sa39 0100111 238000?23ffff sa103 1100111 338000?33ffff sa40 0101000 240000?247fff sa104 1101000 340000?347fff sa41 0101001 248000?24ffff sa105 1101001 348000?34ffff sa42 0101010 250000?257fff sa106 1101010 350000?357fff sa43 0101011 258000?25ffff sa107 1101011 358000?35ffff sa44 0101100 260000?267fff sa108 1101100 360000?367fff sa45 0101101 268000?26ffff sa109 1101101 368000?36ffff sa46 0101110 270000?277fff sa110 1101110 370000?377fff sa47 0101111 278000?27ffff sa111 1101111 378000?37ffff sa48 0110000 280000?287fff sa112 1110000 380000?387fff sa49 0110001 288000?28ffff sa113 1110001 388000?38ffff sa50 0110010 290000?297fff sa114 1110010 390000?397fff sa51 0110011 298000?29ffff sa115 1110011 398000?39ffff sa52 0110100 2a0000?2a7fff sa116 1110100 3a0000?3a7fff sa53 0110101 2a8000?2affff sa117 1110101 3a8000?3affff sa54 0110110 2b0000?2b7fff sa118 1110110 3b0000?3b7fff sa55 0110111 2b8000?2bffff sa119 1110111 3b8000?3bffff sa56 0111000 2c0000?2c7fff sa120 1111000 3c0000?3c7fff sa57 0111001 2c8000?2cffff sa121 1111001 3c8000?3cffff sa58 0111010 2d0000?2d7fff sa122 1111010 3d0000?3d7fff sa59 0111011 2d8000?2dffff sa123 1111011 3d8000?3dffff sa60 0111100 2e0000?2e7fff sa124 1111100 3e0000?3e7fff sa61 0111101 2e8000?2effff sa125 1111101 3e8000?3effff sa62 0111110 2f0000?2f7fff sa126 1111110 3f0000?3f7fff sa63 0111111 2f8000?2fffff sa127 1111111 3f8000?3fffff table 8.8 s29gl064n (models 06, 07, v6, v7) sector addresses (sheet 2 of 2) sector a21?a15 16-bit address range sector a21?a15 16-bit address range
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 29 data sheet 8.8 autoselect mode the autoselect mode provides manufa cturer and device identification, an d sector protection verification, through identifier codes output on dq7?dq0. this mo de is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through th e command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in table 8.9 on page 29 . in addition, when verifying sector protection, the sector address must appear on the appr opriate highest order address bits (see table 8.2 - table 8.8 ). table 8.9 shows the remaining address bits that are don?t care. when all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the hos t system can issue the aut oselect command via the command register, as shown in table 10.1 on page 51 and table 10.3 on page 53 . this method does not require v id . refer to the autoselect command sequence section for more information. legend l = logic low = v il h = logic high = v ih sa = sector address x = don?t care table 8.9 autoselect codes, (high voltage method) description ce# oe# we# a max to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 model number byte# = v ih byte# = v il 01, 02 v1, v2 03, 04 06, 07, v6, v7 manufacturer id : spansion products ll h x xv id x l x l l l 00 x 01h 01h 01h s29gl064n cycle 1 ll h x xv id xlx l l h 22 x 7eh 7eh 7eh cycle 2 h h l 22 x 0ch 10h 13h cycle 3 h h h 22 x 01h 00h (04, bottom boot) 01h (03, top boot) 01h s29gl032n cycle 1 ll h x xv id xlx llh 22 x 7eh 7eh cycle 2 h h l 22 x 1dh 1ah cycle 3 h h h 22 x 00h 00h (04, bottom boot) 01h (03, top boot) sector protection verification ll h saxv id xlxlhl x x 01h (protected), 00h (unprotected) secured silicon sector indicator bit (dq7), wp# protects highest address sector ll h x xv id xlxlhh x x for s29gl064n and s29gl032n: 9a (factory locked), 1a (not factory locked) secured silicon sector indicator bit (dq7), wp# protects lowest address sector ll h x xv id xlxlhh x x for s29gl064n and s29gl032n: 8a (factory locked), 0a (not factory locked)
30 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 8.9 sector protection the device features several levels of sector protection, which can di sable both the program and erase operations in certain sectors: 8.9.1 persistent sector protection a command sector protection method that replac es the old 12 v controlled protection method. 8.9.2 password sector protection a highly sophisticated protection method that requir es a password before changes to certain sectors are permitted 8.9.3 wp# hardware protection a write protect pin that can prevent program or erase operations in the outermost sectors. the wp# hardware protection feature is always avail able, independent of the software managed protection method chosen. 8.9.4 selecting a sect or protection mode all parts default to operate in the pe rsistent sector protection mode. t he customer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non- volatile bits that define which sector protection method is used. if the cu stomer decides to continue using the persistent sector protection method, they must set the persistent sector protection mode locking bit . this permanently sets the part to operate only using pe rsistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit . this permanently sets the part to operate only using password sector protection. it is important to remember that setting either the persistent sector protection mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit is set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or viru s to later set the password mode lo cking bit, which would cause an unexpected shift from the default pe rsistent sector protec tion mode into the password protection mode. the device is shipped with all sectors unprotected. the factory offers the option of programming and protecting sectors at the factory prior to shipping the device through the expressflash? service. contact your sales representative for details. it is possible to determine whether a se ctor is protected or unprotected. see autoselect command sequence on page 42 for details. 8.10 advanced sector protection advanced sector protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. persistent sector protection is a method that replaces the ol d 12v controlled protection method. password sector protection is a highly sophisticated protection me thod that requires a password before changes to certain sectors are permitted.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 31 data sheet 8.11 lock register the lock register consists of 3 bi ts (dq2, dq1, and dq0). these dq2, dq1, dq0 bits of the lock register are programmable by the user. users are not allowed to program both dq2 and dq1 bits of the lock register to the 00 state. if the user tries to program dq2 and dq1 bits of the lock register to the 00 state, the device aborts the lock register back to the default 11 state. the programming time of the lock register is same as the typical word programming time without utilizing the wr ite buffer of the device. during a lock register programming sequence execution, the dq6 toggle bit i toggles until the programmi ng of the lock register has completed to indicate programming status. all lock register bits are readable to allow users to verify lock register statuses. the customer secured silicon sector protection bit is dq0, persistent protection mode lock bit is dq1, and password protection mode lock bit is dq2 are accessible by all users. each of these bits are non-volatile. dq15-dq3 are reserved and must be 1's when the user tries to program th e dq2, dq1, and dq0 bits of the lock register. the user is not required to program dq2, dq1 and dq0 bits of the lock register at the same time. this allows users to lock the secured silicon se ctor and then set the device either permanently into password protection mode or persistent protection mode and then lock the secured silicon sector at separate instances and time frames. ? secured silicon sector protection allows the user to lock the secured silicon sector area ? persistent protection mode lock bit allows the user to set the device permanently to operate in the persistent protection mode ? password protection mode lock bit allows the user to set the device permanently to operate in the password protection mode 8.12 persistent sector protection the persistent sector protection me thod replaces the old 12 v controll ed protection method while at the same time enhancing flexibility by providing three different sector protection states to achieve these states, thre e types of ?bits? are used: 8.12.1 dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardwa re reset, the contents of all dyb bits are in the ?unprotected state?. each dyb is in dividually modifiable through the dyb set command and dyb clear command. when the parts are first shipped, a ll of the persistent protect bits (ppb) are cleared into the unprotected state. the d yb bits and ppb lock bit are defaulted to power up in the cleared state or unprotected state - meaning the all ppb bits are changeable. the protection state for each sector is determined by the logical or of the ppb an d the dyb related to that sector. for the sectors that have th e ppb bits cleared, the dyb bits cont rol whether or not the sector is protected or unprotected. by issuing the dyb set a nd dyb clear command sequences, the dyb bits is protected or unprotected, thus placing each sector in the protected or unprotect ed state. these are the so- called dynamic locked or unlocked stat es. they are called dynamic states bec ause it is very easy to switch back and forth between the protected and un-protected c onditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dyb bits maybe set or cleared as often as needed. the ppb bits allow for a more static, and difficult to change, level of protection. the ppb bits retain their state across power cycles because they are non- table 8.10 lock register dq15-3 dq2 dq1 dq0 don?t care password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit dynamically locked the sector is protect ed and can be changed by a simple command persistently locked a sector is protected and cannot be changed unlocked the sector is unprotected and can be changed by a simple command
32 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet volatile. individual ppb bits are set with a program command but must all be cleared as a group through an erase command. the ppb lock bit adds an ad ditional level of protection. once al l ppb bits are programmed to the desired settings, the ppb lock bit may be set to the ?freeze state?. setting the ppb lock bit to the ?freeze state? disables all program and erase comm ands to the non-volatile ppb bits. in effect, th e ppb lock bit locks the ppb bits into their current st ate. the only way to clear the ppb lock bit to the ?unfreeze state? is to go through a power cycle, or hardware reset. the software reset command do es not clear the ppb lock bit to the ?unfreeze state?. system boot code can determine if any changes to the ppb bits are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock bit to disable any further changes to the ppb bits during system operation. the wp# write protect pin adds a final le vel of hardware protection. when this pin is low it is not possible to change the contents of the wp# protec ted sectors. these sectors generally hold system boot code. so, the wp# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that hav e been persistently locked, and sectors th at are left in the dynamic state. the sectors in the dynamic state are al l unprotected. if there is a need to protect some of them, a simple dyb set command sequence is all that is necessary. t he dyb set and dyb clear commands for the dynamic sectors switch the dyb bits to signify protected and unpr otected, respectively. if th ere is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled to the ?unfreeze state? by either putting the device through a power-cycle, or hardware reset. the ppb bits can then be changed to reflect the desired settings. setting the ppb lock bit once again to the ?freeze state? locks the ppb bits, a nd the device operates normally again. to achieve the best prot ection, execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . 8.12.2 persistent pr otection bit (ppb) a single persistent (non-volatile) protection bit is assi gned to each sector. if a ppb is programmed to the protected state through the ?ppb program? command, that sector is protected from program or erase operations is read-only. if a ppb requires erasure, all of the sector ppb bits must first be erased in parallel through the ?all ppb erase? command. the ?all ppb erase? command preprograms all ppb bits prior to ppb erasing. all ppb bits erase in para llel, unlike progra mming where individual ppb bi ts are programmable. the ppb bits have the same endur ance as the flash memory. programming the ppb bit requires the typical word programming time wit hout utilizing th e write buffer. during a ppb bit programming and all ppb bit erasin g sequence executions, the dq6 toggle bit i toggles until the programming of the ppb bit or erasing of all ppb bits has completed to indicate programming and erasing status. erasing all of the ppb bi ts at once requires typical sector erase time. during the erasing of all ppb bits, the dq3 sector erase timer bi t outputs a 1 to indicate the erasure of all ppb bits are in progress. when the erasure of all ppb bi ts has completed, the dq3 sector erase timer bit outpu ts a 0 to indicate that all ppb bits have been erased. reading the ppb status bit requires the initial access time of the device.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 33 data sheet 8.12.3 persistent protection bit lock (ppb lock bit) a global volatile bit. when set to the ?freeze state?, the ppb bits cannot be changed. when cleared to the ?unfreeze state?, the ppb bits are changeable. there is on ly one ppb lock bit per device. the ppb lock bit is cleared to the ?unfreeze state? after power-up or hardware reset. there is no command sequence to unlock or ?unfreeze? the ppb lock bit. configuring the ppb lock bit to the freeze state requires approximatel y 100ns. reading th e ppb lock status bit requires the initial access time of the device. table 8.11 contains all possible combinations of the dyb bi t, ppb bit, and ppb lock bit relating to the status of the sector. in summary, if the ppb bit is set, and the ppb lock bit is set, the se ctor is prot ected and the protection cannot be remo ved until the next power cycle or hardware reset clears the ppb lock bit to ?unfreeze state?. if the ppb bit is cl eared, the sector can be dynamically locked or unlocked. the dyb bit then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the pr otected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the devic e returns to read mode without having erased the protected sector. the prog ramming of the dyb bit, ppb bit, and ppb lock bit for a given sector can be verified by writing a dyb status read, ppb status read, and ppb lo ck status read commands to the device. the autoselect sector protection verification outputs th e or function of the dyb bit and ppb bit per sector basis. when the or function of the d yb bit and ppb bit is a 1, the sector is either protec ted by dyb or ppb or both. when the or functi on of the dyb bit and ppb bit is a 0, the sector is unprotected through both the dyb and ppb. 8.13 persistent protection mode lock bit like the password protection mode lock bit, a persistent protection mode lock bit exists to guarantee that the device remain in software sector protection. once programmed, the persistent protection mode lock bit prevents programming of the password protection mo de lock bit. this guarantees that a hacker could not place the device in password protection mode. the pass word protection mode lock bit resides in the ?lock register?. table 8.11 sector protection schemes protection states sector state dyb bit ppb bit ppb lock bit unprotect unprotect unfreeze unprotected ? ppb and dyb are changeable unprotect unprotect freeze unprotected ? ppb not changeable, dyb is changeable unprotect protect unfreeze protected ? ppb and dyb are changeable unprotect protect freeze protected ? ppb not changeable, dyb is changeable protect unprotect unfreeze protected ? ppb and dyb are changeable protect unprotect freeze protected ? ppb not changeable, dyb is changeable protect protect unfreeze protected ? ppb and dyb are changeable protect protect freeze protected ? ppb not changeable, dyb is changeable
34 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 8.14 password sector protection the password sector protection method allows an even higher level of security th an the persistent sector protection method. there are two ma in differences between the persis tent sector protection and the password sector protection methods: ? when the device is first powered on, or comes out of a reset cycle, th e ppb lock bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. ? the only means to clear and unfreeze the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection meth od is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (o tp) region outside of the flash memory. once the password protection mode lock bit is set, the passwo rd is permanently set with no means to read, program, or erase it. the password is used to clear and unfreeze the ppb lock bit. the password unlock command must be written to the flash, along with a password. th e flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared to the unfreezed state , and the ppb bits can be altered. if t hey do not match, the flash de vice does nothing. there is a built-in 2 s delay for each password check after the valid 64-bi t password is entered for the ppb lock bit to be cleared to the ?unfreezed state?. this delay is in tended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 8.15 password and password protection mode lock bit in order to select the password se ctor protection method, the customer must first program the password. the factory recommends that the password be somehow co rrelated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password read operations. once the desired pa ssword is programmed in, the customer must then set the password protection mode lock bit. this operation achieves two objectives: 1. it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2. it also disables all further commands to the passw ord region. all program, and read operations are ignored. both of these objectives are important, and if not care fully considered, may lead to unrecoverable errors. the user must be sure that the password sector protec tion method is desired when programming the password protection mode lock bit. more importantly, the user must be sure that the password is correct when the password protection mode lock bit is programmed. due to the fact that read operations are disabled, there is no means to read what the password is afterwards. if the password is lost after programming the password protection mode lock bit, there is no way to clear and unfr eeze the ppb lock bit. the password protection mode lock bit, once programmed, prevents reading the 64-b it password on the dq bus and further password programming. the password protection mode lock bit is not erasable. once password protection mode lock bit is programmed, the persistent protection mode lock bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 8.16 64-bit password the 64-bit password is located in its own memory spac e and is accessible through the use of the password program and password read commands. the password function works in conjunction with the password protection mode lock bit, which when programmed, pr events the password read command from reading the contents of the password on the pins of the device.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 35 data sheet 8.17 persistent protection bit lock (ppb lock bit) a global volatile bit. the ppb lock bit is a volatile bit that reflec ts the state of the pa ssword protection mode lock bit after power-up reset. if the password prot ection mode lock bit is also programmed after programming the password, the password unlock command must be issued to clear and unfreeze the ppb lock bit after a hardware reset (r eset# asserted) or a po wer-up reset. successful execution of the password unlock command clears and unfreezes the ppb lock bit, allo wing for sector ppb bits to be modified. without issuing the password unlock command, while asserting reset#, taking the device through a power-on reset, or issu ing the ppb lock bit set command sets the ppb lock bit to a the ?freeze state?. if the password protection mode lock bit is not progra mmed, the device defaults to persistent protection mode. in the persistent protection mode , the ppb lock bit is cleared to the unfreeze state after power-up or hardware reset. the ppb lock bit is set to the freeze state by issuing the ppb lock bit set command. once set to the freeze state the only means for clearing the ppb lock bit to the ?unfreeze state? is by issuing a hardware or power-up reset. the password unlock comm and is ignored in persistent protection mode. reading the ppb lock bit requires a 200ns access time. 8.18 secured silicon sect or flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 bytes in length, and uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is pe rmanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ens ures the security of the esn once the product is shipped to the field. the factory offers the device with th e secured silicon sector either customer lockable (standard shipping option) or factory locked (contact an amd sales repr esentative for ordering information). the customer- lockable version is shipped with the secured silicon se ctor unprotected, allowing customers to program the sector after receiving the device. the customer-lo ckable version also has the secured silicon sector indicator bit permanently set to a 0 . the factory-locked version is always protected when shipped from the factory, and has the secured silicon sect or indicator bit permanently set to a 1 . thus, the secured silicon sector indicator bit prevents customer-lockable device s from being used to replac e devices that are factory locked . the secured silicon sector address space in this device is allocated as follows: the system accesses the secured silicon sector through a command sequence (see write protect (wp/ acc#) on page 36 ). after the system has written the enter se cured silicon sector command sequence, it may read the secured silicon sector by using the addresse s normally occupied by the first sector (sa0). this mode of operation continues until the system issues the exit secur ed silicon sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. secured silicon sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
36 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 8.18.1 customer lockable: se cured silicon sector not programmed or protected at the factory unless otherwise specified, the device is shipped su ch that the customer may program and protect the 256- byte secured silicon sector. the system may program the secured silicon sector using the write-buffer, a ccelerated and/or unlock bypass methods, in addition to the standard programming command sequence. see command definitions on page 41 . programming and protecting the secured silicon sector must be used with caution since, once protected, there is no procedure available for un protecting the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. the secured silicon sector area can be prot ected using one of the following procedures: ? write the three-cycle enter secure d silicon sector region command. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm. once the secured silicon sector is programmed, locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing within the remainder of the array. 8.18.2 factory locked: secur ed silicon sector program med and protected at the factory in devices with an esn, the secured silicon sector is pr otected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please co ntact your sales representative for details on ordering esn factory locked devices. customers may opt to have their code programmed by the factory through the expr essflash service (express flash factory locked). the devices are then shipped from the factory with the secured silicon sector permanently locked. contact your sales representative for details on using the expressflash service. 8.19 write protect (wp/acc#) the write protect function provides a hardware method of protecting the fi rst or last sector without using v id . write protect is one of two functi ons provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables pr ogram and erase functions in the first or last sector independently of whether th ose sectors were protected or unprote cted. note that if wp#/acc is at v il when the device is in the standby mode, the maximu m input load current is increased. see the table in dc characteristics on page 62 . if the system asserts v ih on the wp#/acc pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in sector protection on page 30 . note that wp/acc# contains an internal pullup; when unconnected, wp/acc# is at v ih . 8.20 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10.1 on page 51 and table 10.3 on page 53 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which migh t otherwise be caused by spuri ous system level si gnals during v cc power-up and power-down transitions, or from system noise. 8.20.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the cont rol pins to prevent uni ntentional writes when v cc is greater than v lko .
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 37 data sheet 8.20.2 write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 8.20.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 8.20.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is aut omatically reset to the read mode on power-up. 9. common flash memory interface (cfi) the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device -independent, jedec id-independent, and forward- and backward-compatible for the specifie d flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi info rmation at the addresses given in table 9.1 on page 37 ? table 9.4 on page 40 . to terminate reading cfi dat a, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 9.1 on page 37 ? table 9.4 on page 40 . the system must write the rese t command to return the device to reading array data. for further information, please refer to the cfi specification and cfi pub lication 100. alter natively, contact your sales representative for copies of these documents. table 9.1 cfi query identification string addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
38 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet note cfi data related to v cc and time-outs may differ from actual v cc and time-outs of the product. please consult the ordering information tables to obtain the v cc range for particular part numbers. please consult the erase and programming performance table for typical timeout specifications. table 9.2 system interface string addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h reserved for future use 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0003h max. timeout for byte/word program 2 n times typical. 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 39 data sheet table 9.3 device geometry definition addresses (x16) addresses (x8) data description 27h 4eh 00xxh device size = 2 n byte 0017h = 64 mb, 0016h = 32 mb 28h 29h 50h 52h 000xh 0000h flash device interface descripti on (refer to cfi publication 100) 0001h = x16-only bus devices 0002h = x8/x16 bus devices 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 00xxh number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 000xh 00x0h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 007fh, 0000h, 0000h, 0001h = 64 mb (01, 02, 06, 07, v1, v2, v6, v7) 0007h, 0000h, 0020h, 0000h = 64 mb (03, 04) 003fh, 0000h, 0000h, 0001h = 32 mb (01, 02, v1, v2) 0007h, 0000h, 0020h, 0000h = 32 mb (03, 04) 31h 32h 33h 34h 60h 64h 66h 68h 00xxh 0000h 0000h 000xh erase block region 2 information (refer to cfi publication 100) 0000h, 0000h, 0000h, 0000h = 64 mb (01, 02, 06, 07, v1, v2, v6, v7) 007eh, 0000h, 0000h, 0001h = 64 mb (03, 04) 0000h, 0000h, 0000h, 0000h = 32 mb (01, 02, v1, v2) 003eh, 0000h, 0000h, 0001h = 32 mb (03, 04) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
40 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet table 9.4 primary vendor-specific extended query addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 00xxh address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7- 2) 0100b = 110 nm mirrorbit 0011h = x8-only bus devices 0010h = all other devices 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in smallest sector 48h 90h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0008h sector protect/unprotect scheme 0008h = advanced sector protection 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0002h page mode type 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 00xxh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 41 data sheet 10. command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. table 10.1 on page 51 and table 10.3 on page 53 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens firs t. refer to the ac charac teristics section for timing diagrams. 10.1 reading array data the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data. the device is ready to read array dat a after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, th e device enters the erase-suspend-read mode, after which the system can read data from any non-erase- suspended sector. after completing a programming operation in the erase suspend mode, the system may on ce again read array data with the same exception. see erase suspend/erase resume commands on page 50 for more information. the system must issue the reset command to retu rn the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the de vice is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations sect ion for more information. the read-only operations? ac characteristics on page 64 provide the read parameters, and figure 15.2 on page 65 shows the timing diagram. 10.2 reset command writing the reset command resets the device to the r ead or erase-suspend-read mode . address bits are don?t cares for this command. the reset command may be written between the s equence cycles in an erase command sequence before erasing begins. this resets the device to the read mo de. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be writt en between the s equence cycles in a progra m command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase su spend mode, writing the reset comma nd returns the device to the erase- suspend-read mode. once programming begins, howe ver, the device ignores reset commands until the operation is complete. the reset command may be written between the sequ ence cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspe nd mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer progr amming operation, the system must write the write-to- buffer-abort reset command se quence to reset the device for the next operation.
42 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 10.3 autoselect command sequence the autoselect command sequence allows the host sys tem to read several identifier codes at specific addresses: note the device id is read over three cycles. sa = sector address the autoselect command se quence is initiated by first writing on unlock cycle (two cycl es). this is followed by a third write cycle that contains the autoselect co mmand. the device then enters the autoselect mode. the system may read at any address any number of ti mes without initiating another autoselect command sequence: the system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in erase suspend). 10.4 enter/exit secured s ilicon sector command sequence the secured silicon sector region provides a secure d data area containing an 8-word/16-byte random electronic serial number (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command seque nce. the device continues to access the secured silicon sector region until the system issues the four -cycle exit secured silicon sector command sequence. the exit secured silicon sector command sequenc e returns the device to normal operation. table 10.1 on page 51 and table 10.3 on page 53 show the address and data r equirements for both command sequences. see also secured silicon sector flash memory region on page 35 for further information. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. 10.4.1 word program command sequence programming is a four-bus-cycle o peration. the program co mmand sequence is initiated by writing two unlock write cycles, followed by th e program set-up command. the pr ogram address and data are written next, which in turn initiate the embedded progra m algorithm. the system is not required to provide further controls or timings. the device autom atically provides internally generated program pulses and verifies the programmed cell margin. table 10.1 on page 51 and table 10.3 on page 53 show the address and data requirements for the word program command sequence, respectively. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the prog ram operation by using dq7 or dq6. refer to the write operation status sect ion for information on these status bits. any commands written to the device during the embe dded program algorithm are ignored. note that the secured silicon sector, autoselect, and cfi functions are unavaila ble when a program operation is in progress. note that a hardware reset immediately terminates the program operati on. the program command sequence should be reinitiated once the device returns to t he read mode, to ensure data integrity. programming is allowed in any sequence of address locations and across sector boundaries. programming to the same word address multiple times without interveni ng erases (incremental bit programming) requires a modified programming method. for such application requirements, please contact your local spansion representative. word programming is supported for backw ard compatibility with existi ng flash driver software and for occasional writing of individual words. use of write buffer programmi ng (see below) is strongly recommended for general programming use when more than a few words are to be programmed. the effective word programming time using write buffer progr amming is approximately fo ur times shorter than the single word programming time. identifier code a7:a0 (x16) a6:a-1 (x8) manufacturer id 00h 00h device id, cycle 1 01h 02h device id, cycle 2 0eh 1ch device id, cycle 3 0fh 1eh secured silicon sector factory protect 03h 06h sector protect verify (sa)02h (sa)04h
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 43 data sheet any bit in a word cannot be programmed from 0 back to a 1 . attempting to do so may cause the device to set dq5=1, or cause dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read shows that the data is still 0 . only erase operations can convert a 0 to a 1 . 10.4.2 unlock bypa ss command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. the unlock bypass command s equence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock by pass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass mode command sequence is all that is required to program in this mode. the first cycle in this seque nce contains the unlock by pass program command, a0h; the second cycle contains the progr am address and data. addi tional data is prog rammed in the same manner. this mode dispenses with the initial two un lock cycles required in the standard program command sequence, resulting in faster total programming time. table 10.1 on page 51 and table 10.3 on page 53 show the requirements fo r the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle mu st contain the data 90h. th e second cycle must contain the data 00h. the device then returns to the read mode. 10.4.3 write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programm ing time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer lo ad command written at the sector address in which programming occurs. the fourth cycle writes the sect or address and the number of word locations, minus one, to be programmed. for example, if the system programs six unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses are loaded with data and therefore when to expect the program buffer to flas h command. the number of loca tions to program cannot exceed the size of the write buffer or the operation aborts. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is selected by address bits a max ?a 4 . all subsequent address/data pairs must fa ll within the selected-write-buffer-page. the system then writes the remaining address/data pair s into the write buffer. wr ite buffer locations may be loaded in any order. the write-buffer-page address must be the same for all ad dress/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed acro ss multiple write-buffer pages.) this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation aborts. note that if a write buffer address location is l oaded multiple times, the a ddress/data pair counter is decremented for every data lo ad operation. the host system must therefore account for loading a wr ite-buffer location more than once. the counter decrements for each data load operation, not for each unique write- buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address is programmed. once the specified number of writ e buffer locations are loaded, the system must then wr ite the program buffer to flash command at the se ctor address. any other address and data combination aborts the write buffer programming operation. the device then b egins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device stat us during write buffer programming. the write-buffer programming operation can be sus pended using the standard program suspend/resume commands. upon successful completion of the write buff er programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load command.
44 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet ? write an address/data pair to a different write-buffe r-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the conf irm command after t he specified number of data load cycles. the abort condition is indicated by dq1 = 1 , dq7 = data# (for the last ad dress location loaded), dq6 = toggle, and dq5= 0 . a write-to-buffer-abort reset command sequence must be written to reset the device for the next operation. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. this flash device is capable of handling multiple write buffer programming operations on the same write buffer address rang e without intervening erases. for applications requiring incremental bit programming, a modified programming method is required; please contact your local spansion representative. any bit in a write buffer address range cannot be programmed from 0 back to a 1 . attempting to do so may cause the device to set dq5=1, of cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succ eeding read shows that the data is still 0 . only erase operations can convert a 0 to a 1 . 10.4.4 accelerated program the device offers accelerated program operations through the wp#/acc or acc pin depending on the particular product. when the system asserts v hh on the wp#/acc or acc pin. the device uses the higher voltage on the wp#/acc or acc pi n to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. wp# contains an internal pullup; when unconnected, wp# is at v ih . figure 10.1 on page 45 illustrates the algorithm for the program operation. refer to the erase and program operations? ac characteristics on page 64 for parameters, and figure 15.3 on page 65 for timing diagrams.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 45 data sheet figure 10.1 write buffer programming operation notes 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= 1 , then the device failed. if this flow chart location was reached because dq1= 1 , then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1= 1 , write the write-buffer-programming-abort-reset command. if dq5= 1 , write the reset command. 4. see table 10.1 on page 51 and table 10.3 on page 53 for command sequences required for write buffer programming. write ?write to b u ffer ? comm a nd a nd s ector addre ss write n u m b er of a ddre ss e s to progr a m min us 1(wc) a nd s ector addre ss write progr a m bu ffer to fl as h s ector a ddre ss write fir s t a ddre ss /d a t a write to a different s ector a ddre ss fail or abort pa ss re a d dq7 - dq0 a t l as t lo a ded addre ss re a d dq7 - dq0 with a ddre ss = l as t lo a ded addre ss write next a ddre ss /d a t a p a ir wc = wc - 1 wc = 0 ? p a rt of ? write to b u ffer ? comm a nd s e qu ence ye s ye s ye s ye s ye s ye s no no no no no no a b ort write to b u ffer oper a tion? dq7 = d a t a ? dq7 = d a t a ? dq5 = 1? dq1 = 1? write to bu ffer aborted. m us t write ? write-to- bu ffer a b ort re s et ? comm a nd s e qu ence to ret u rn to re a d mode. (note 2) (note 3 ) (note 1)
46 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet figure 10.2 program operation note see table 10.1 on page 51 and table 10.3 on page 53 for program command sequence. 10.5 program suspend/program resume command sequence the program suspend command allows the system to inte rrupt a programming operatio n or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program suspend command is written during a programming proc ess, the device halts the program operation within 20 s maximum and updates the status bits. addresses ar e not required when writing the program suspend command. after the programming operation is suspended, the s ystem can read array data from any non-suspended sector. the program suspend command may also be i ssued during a programming operation while an erase is suspended. in this case, data may be read from an y addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector ar ea (one-time program area), then user must use the proper command sequences to enter and exit this regi on. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. wh en the device exits the autoselect mode, the device reverts to the pr ogram suspend mode, and is ready for another valid operation. see autoselect command sequence on page 42 for more information. after the program resume command is written, th e device reverts to prog ramming. the system can determine the status of the program operation using the dq7 or dq6 stat us bits, just as in the standard program operation. see write operation status on page 55 for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device resumes programming. s ta rt write progr a m comm a nd s e qu ence d a t a poll from s y s tem verify d a t a ? no ye s l as t addre ss ? no ye s progr a mming completed increment addre ss em b edded progr a m a lgorithm in progre ss
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 47 data sheet figure 10.3 program suspend/program resume 10.6 chip erase command sequence chip erase is a six bus cycle operatio n. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the emb edded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 10.1 on page 51 and table 10.3 on page 53 show the address and data requirements for t he chip erase command sequence. when the embedded erase algorithm is complete, the dev ice returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by us ing dq7, dq6, or dq2. refer to write operation status on page 55 for information on these status bits. any commands written during the chip erase op eration are ignored. however, note that a hardware reset immediately terminates the erase operation. if this occurs, the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. figure 10.4 on page 49 illustrates the algorithm for the erase operation. refer to table 15.3 on page 67 for parameters, and figure 15.7 on page 69 for timing diagrams. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no ye s write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 20 s
48 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 10.7 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be er ased, and the sector erase command. table 10.1 on page 51 and table 10.3 on page 53 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase commands ma y be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be le ss than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may no t be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sect or erase command is written. any command other than sector erase or erase suspend duri ng the time-out peri od resets the device to the read mode. note that the secured silicon sector, autoselect, and cfi functions are unava ilable when an erase operation is in progress. the system must rewrite the command sequenc e and any additional addresses and commands. the system can monitor dq3 to determ ine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from th e rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the st atus of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for informat ion on these status bits. once the sector erase operation begins, only the eras e suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. figure 10.4 on page 49 illustrates the algorithm for the erase operation. refer to table 15.3 on page 67 for parameters, and figure 15.7 on page 69 for timing diagrams.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 49 data sheet figure 10.4 erase operation notes 1. see table 10.1 and table 10.3 for program command sequence. 2. see the section on dq3 for information on the sector erase timer. s ta rt write er as e comm a nd s e qu ence (note s 1, 2) d a t a poll to er as ing b a nk from s y s tem d a t a = ffh? no ye s er asu re completed em b edded er as e a lgorithm in progre ss
50 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 10.8 erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector eras e operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written duri ng the chip erase operation or embedded program algorithm. when the erase suspend command is written during the se ctor erase operation, the device requires a typical of 5 s ( maximum of 20 s) to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device i mmediately terminates the time-out period and suspends the erase operation. after the erase operation is suspended, the device en ters the erase-suspend-read mode. the system can read data from or program data to any sect or not selected for erasure. (the device erase suspends all sectors selected for erasure.) reading at any addre ss within erase-suspended se ctors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to write operation status on page 55 for information on these status bits. after an erase-suspended program operation is comple te, the device returns to the erase-suspend-read mode. the system can determine the st atus of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to write operation status on page 55 for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode on page 29 and autoselect command sequence on page 42 sections for details. to resume the sector erase operation, the system must write the erase re sume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip resumes erasing. during an erase operation, this flash device performs mu ltiple internal operations which are invisible to the system. when an erase operation is suspended, any of th e internal operations that were not fully completed must be restarted. as such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress is impeded as a function of the number of suspends. the result is a longer cumulative erase time than without suspends. note that the additional suspends do not affect device reliability or future performance. in most system s rapid erase/suspend activity occurs only briefly. in such cases, erase performance is not sign ificantly impacted.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 51 data sheet 10.9 command definitions table 10.1 command definitions (x16 mode, byte# = v ih ) command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth read (note 5) 1rard reset (note 6) 1xxxf0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 8) 6 555 aa 2aa 55 555 90 x01 227e x0e (note 18) x0f (note 18) device id 4 555 aa 2aa 55 555 90 x01 (note 17) secured silicon sector factory protect 4 555 aa 2aa 55 555 90 x03 (note 9) sector protect verify (note 10) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secured silicon sector region 3 555 aa 2aa 55 555 88 exit secured silicon sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 12) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 15) 1xxxb0 program/erase resume (note 16) 1xxx30 cfi query (note 17) 15598 legend x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uni quely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table 8.1 on page 17 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or 2aa as shown in table, address bits above a11 and data bits above dq7 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. reset command is required to return to read mode (or to erase-suspend- read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. except for rd, pd and wc. see autoselect command sequence on page 42 for more information. 8. for s29gl064n and s29gl032n, device id must be read in three cycles. 9. refer to table 8.9 on page 29 for data indicating secured silicon sector factory protect status. 10. data is 00h for an unprotected sector and 01h for a protected sector. 11. total number of cycles in command sequence is determined by number of words written to write buffer. maximum number of cycles in command sequence is 21, including program buffer to flash command. 12. command sequence resets device for next command after aborted write- to-buffer operation. 13. unlock bypass command is required prior to unlock bypass program command. 14. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 15. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode . erase suspend command is valid only during a sector erase operation. 16. erase resume command is valid only during erase suspend mode. 17. command is valid when device is ready to read array data or when device is in autoselect mode. 18. refer to table 8.9 on page 29 , for individual device ids per device density and model number.
52 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet table 10.2 sector protection commands (x16) command sequence (notes) cycles bus cycles (notes 2 ? 4 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data lock register bits command set entry (note 5) 3 555 aa 2aa 55 555 40 program (note 6) 2 xx a0 xxx data read (note 6) 1 00 data command set exit (note 7) 2xx 90 xx 00 password protection command set entry (note 5) 3 555 aa 2aa 55 555 60 program (note 8) 2xx a0 pwaxpwdx read (note 9) 4 xxx pwd0 01 pwd1 02 pwd2 03 pwd3 unlock (note 10) 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 command set exit (note 7) 2xx 90 xx 00 non-volatile sector protection (ppb) command set entry (note 5) 3 555 aa 2aa 55 555 c0 ppb program (note 11) 2xx a0 sa 00 all ppb erase (notes 11 , 12 ) 2xx 80 00 30 ppb status read 1 sa rd(0) command set exit (note 7) 2xx 90 xx 00 global volatile sector protection freeze (ppb lock) command set entry (note 5) 3 555 aa 2aa 55 555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 xxx rd(0) command set exit (note 7) 2xx 90 xx 00 volatile sector protection (dyb) command set entry (note 5) 3 555 aa 2aa 55 555 e0 dyb set 2 xx a0 sa 00 dyb clear 2 xx a0 sa 01 dyb status read 1 sa rd(0) command set exit (note 7) 2xx 90 xx 00 l egen d x = don?t care. ra = address of the memory location to be read. sa = sector address. any address that falls within a specified sector. see ta bl e s 8.2 ? 8.8 for sector address ranges. pwa = password address. address bits a1 and a0 are used to select each 16- bit portion of the 64-bit entity. pwd = password data. rd(0) = dq0 protection indicator bit. if protected, dq0 = 0. if unprotected, dq0 = 1. notes 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. no unlock or command cycles required when bank is reading array data. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is required for reading password. 10. password may be unlocked or read in any order. unlocking requires the full password (all seven cycles). 11. acc must be at v ih when setting ppb or dyb. 12. ?all ppb erase? command pre-programs all ppbs before erasure to prevent over-erasure.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 53 data sheet table 10.3 command definitions (x8 mode, byte# = v il ) command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1rard reset (note 7) 1xxx f0 autoselect (note 8) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id (note 9) 6 aaa aa 555 55 aaa 90 x02 7e x1c (note 17) x1e (note 17) device id 4 aaa aa 555 55 aaa 90 x02 (note 10) secured silicon sector factory protect 4 aaa aa 555 55 aaa 90 x06 sector protect verify (note 11) 4 aaa aa 555 55 aaa 90 (sa)x04 00/01 enter secured silicon sector region 3 aaa aa 555 55 aaa 88 exit secured silicon sector region 4 aaa aa 555 55 aaa 90 xxx 00 program 4 aaa aa 555 55 aaa a0 pa pd write to buffer (note 12) 3 aaa aa 555 55 sa 25 sa bc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 13) 3 aaa aa 555 55 aaa f0 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 unlock bypass aaa aa 555 55 aaa 20 unlock bypass program xxx a0 pa pd unlock bypass reset xxx 90 xxx 00 program/erase suspend (note 14) 1 xxx b0 program/erase resume (note 15) 1xxx 30 cfi query (note 16) 1aa 98 legend x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uni quely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. bc = byte count. number of write buffer locations to load minus 1. notes 1. see table 8.1 on page 17 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or aaa as shown in table, address bits above a11 are don?t care. 5. unless otherwise noted, address bits a21?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. reset command is required to return to read mode (or to erase-suspend- read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 8. fourth cycle of autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see autoselect command sequence on page 42 for more information. 9. for s29gl064n and s29gl032a device id must be read in three cycles. 10. refer to table 8.9 on page 29 , for data indicating secured silicon sector factory protect status. 11. data is 00h for an unprotected sector and 01h for a protected sector. 12. total number of cycles in command sequence is determined by number of bytes written to write buffer. maximum number of cycles in command sequence is 37, including program buffer to flash command. 13. command sequence resets device for next command after aborted write- to-buffer operation. 14. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode . erase suspend command is valid only during a sector erase operation. 15. erase resume command is valid only during erase suspend mode. 16. command is valid when device is ready to read array data or when device is in autoselect mode. 17. refer to table 8.9 on page 29 , for individual device ids per device density and model number.
54 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet table 10.4 sector protection commands (x8) command sequence (notes) cycles bus cycles (notes 2 ? 5 ) 1st/8th 2nd/9th 3rd/10th 4th/11th 5th 6th 7th addr data addr data addr data addr data addr data addr data addr data lock register bits command set entry (note 5) 3 aaa aa 555 55 aaa 40 program (note 6) 2 xxx a0 xxx data read (note 6) 1 00 data command set exit (note 7) 2 xxx 90 xxx 00 password protection command set entry (note 5) 3 aaa aa 555 55 aaa 60 program (note 8) 2 xxx a0 pwax pwdx read (note 9) 8 00 pwd0 01 pwd1 02 pwd2 03 pwd3 04 pwd4 05 pwd5 06 pwd6 07 pwd7 unlock (note 10) 11 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 04 pwd4 05 pwd5 06 pwd6 07 pwd7 00 29 command set exit (note 7) 2xx 90 xx 00 non-volatile sector protection (ppb) command set entry (note 5) 3 aaa aa 555 55 aaa c0 ppb program (note 11) 2 xxx a0 sa 00 all ppb erase (notes 11 , 12 ) 2 xxx 80 00 30 ppb status read 1 sa rd(0) command set exit (note 7) 2 xxx 90 xxx 00 global volatile sector protection freeze (ppb lock) command set entry (note 5) 3 aaa aa 555 55 aaa 50 ppb lock bit set 2 xxx a0 xxx 00 ppb lock bit status read 1 xxx rd(0) command set exit (note 7) 2 xxx 90 xx 00 volatile sector protection (dyb) command set entry (note 5) 3 aaa aa 555 55 aaa e0 dyb set 2 xxx a0 sa 00 dyb clear 2 xxx a0 sa 01 dyb status read 1 sa rd(0) command set exit (note 7) 2 xxx 90 xxx 00 l egen d x = don?t care. ra = address of the memory location to be read. sa = sector address. any address that falls within a specified sector. see ta bl e s 8.2 ? 8.8 for sector address ranges. pwa = password address. address bits a1 and a0 are used to select each 16- bit portion of the 64-bit entity. pwd = password data. rd(0) = dq0 protection indicator bit. if protected, dq0 = 0. if unprotected, dq0 = 1. notes 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. no unlock or command cycles required when bank is reading array data. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is required for reading password. 10. password may be unlocked or read in any order. unlocking requires the full password (all seven cycles). 11. acc must be at v ih when setting ppb or dyb. 12. ?all ppb erase? command pre-programs all ppbs before erasure to prevent over-erasure.
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 55 data sheet 10.10 write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 10.5 on page 60 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or is completed. 10.11 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for appro ximately 1 s, then the device returns to the read mode. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete , or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the dev ice returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protecte d. however, if the system reads dq 7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if t he device completed the program or er ase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. va lid data on dq0?dq7 appears on successive read cycles. table 10.5 on page 60 shows the outputs for data# polling on dq7. figure 10.5 on page 56 shows the data# polling algorithm. figure 15.8 on page 69 shows the data# polling timing diagram.
56 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet figure 10.5 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 10.12 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin wh ich indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-dra in output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the devic e is actively erasing or programmi ng. (this includes programming in the erase suspend mode.) if the output is high (ready), the dev ice is in the read mode, the standby mode, or in the erase-suspend-read mode. table 10.5 on page 60 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq15?dq0 addr = va read dq15?dq0 addr = va dq7 = data? start
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 57 data sheet 10.13 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device entered the er ase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the se ctor erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce # to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all se lected sectors are protected, the embedded erase algorithm erases the unprotected sect ors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see dq7: data# polling on page 55 ). if a program address falls within a protected sector, dq6 toggles for approximatel y 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 10.5 on page 60 shows the outputs for toggle bit i on dq6. figure 10.6 on page 58 shows the toggle bit algorithm. figure 15.9 on page 70 shows the toggle bit timing diagrams. figure 15.10 on page 70 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii on page 58 .
58 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet figure 10.6 toggle bit algorithm note the system should recheck the toggle bit even if dq5 = 1 because the toggle bit may st op toggling as dq5 changes to 1 . see the subsections on dq6 and dq2 for more information. 10.14 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that were selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indica tes whether the device is actively erasing, or is in erase su spend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 10.5 on page 60 to compare outputs for dq2 and dq6. s ta rt no ye s ye s dq5 = 1? no ye s toggle bit = toggle? no progr a m/er as e oper a tion not complete, write re s et comm a nd progr a m/er as e oper a tion complete re a d dq7?dq0 toggle bit = toggle? re a d dq7?dq0 tw i c e re a d dq7?dq0
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 59 data sheet figure 10.6 on page 58 shows the toggle bit algo rithm in flowchart form. figure 15.9 on page 70 shows the toggle bit timing diagram. figure 15.10 on page 70 shows the differences between dq2 and dq6 in graphical form. 10.15 reading toggle bits dq6/dq2 refer to figure 10.6 on page 58 for the following discussi on. whenever the system in itially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the t oggle bit is not toggling, the device completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whet her the value of dq5 is high (see the section on dq5) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device successfully completed the program or erase operation. if it is still toggling, the device did not comp leted the operation successf ully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 10.6 on page 58 ). 10.16 dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 . indicating that the progr am or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the timi ng limit is exceeded, dq5 produces a 1 . in all these cases, the syst em must write the reset command to retu rn the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). 10.17 dq3: sector erase timer after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure began. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time -out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1 . if the time between additional sector erase commands from the system can be assumed to be le ss than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further comma nds (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command is accepted, the system software should ch eck the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on t he second status check, the last command might not have been accepted. table 10.5 on page 60 shows the status of dq3 relati ve to the other status bits.
60 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 10.18 dq1: write-to-buffer abort dq1 indicates whether a write-to-b uffer operation was abor ted. under these cond itions dq1 produces a 1 . the system must issue the write-to-buffer-abort-reset command sequence to return the device to reading array data. see write buffer on page 18 for more details. notes 1. dq5 switches to 1 when an embedded program, embedded erase, or write-to-buffer operation exceeded the maximum timing limits. refer to the sectio n on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to 1 when the device aborts the write-to-buffer operation. table 10.5 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 61 data sheet 11. absolute maximum ratings notes 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 11.2 . 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the devi ce. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 11.1 maximum negative overshoot waveform figure 11.2 maximum positive overshoot waveform 12. operating ranges notes 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. v io input voltage always must be lower than v cc input voltage. parameter rating storage temperature, plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground v cc (note 1) ?0.5 v to +4.0 v a9, oe#, acc and reset# (note 2) ?0.5 v to +12.5 v all other pins (note 1) ?0.5 v to v cc +0.5 v output short circuit current (note 3) 200 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v parameter range ambient temperature (t a ), industrial (i) devices ?40c to +85c supply voltages v cc for full voltage range +2.7 v to +3.6 v v io +1.65 to +3.6 v
62 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 13. dc characteristics notes 1. i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded erase, embedded program, or write buffer programming is in progress. 3. not 100% tested. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 5. v io = 1.65?1.95 v or 2.7?3.6 v. 6. v cc = 3 v and v io = 3 v or 1.8 v. when v io is at 1.8 v, i/os cannot operate at 3 v. table 13.1 dc characteristics, cmos compatible parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (note 1) v in = v ss to v cc , v cc = v cc max #wp/acc: 2.0 a a others: 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc initial read current (note 1) ce# = v il, oe# = v ih , v cc = v cc max, f = 1 mh 610 ma ce# = v il, oe# = v ih , v cc = v cc max, f = 5 mhz 25 30 ce# = v il, oe# = v ih , v cc = v cc max, f = 10 mhz 45 50 i cc2 v cc intra-page read current (note 1) ce# = v il, oe# = v ih , v cc = v cc max f = 10 mhz 110 ma ce# = v il, oe# = v ih , v cc = v cc max f = 33 mh 520 i cc3 v cc active erase/program current (notes 2 , 3 ) ce# = v il, oe# = v ih , v cc = v cc max 50 60 ma i cc4 v cc standby current v cc = v cc max ; v io = v cc ; oe# = v ih ; v il = (v ss +0.3v) / ?0.1v; ce#, reset# = v cc 0.3 v 15a i cc5 v cc reset current v cc = v ccmax , v io = v cc , v il = (v ss +0.3v) / ?0.1v; reset# = v ss 0.3 v 15a i cc6 automatic sleep mode (note 4) v cc = v ccmax , v io = v cc , v ih = v cc 0.3 v; v il = (v ss +0.3v) / ?0.1v; wp#/acc = v ih 15a i acc acc accelerated program current ce# = v il , oe# = v ih , v cc = v cc max, wp#/acc = v ih wp#/ acc 10 20 ma v cc 50 60 ma v il input low voltage 1 (note 5) ?0.1 0.3 x v io v v ih input high voltage 1 (note 5) 0.7 v io v io + 0.3 v v hh voltage for acc erase/program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage (note 5) i ol = 100 a 0.15 x v io v v oh1 output high voltage (note 5) i oh = ?100 a 0.85 v io v v oh2 v lko low v cc lock-out voltage (note 3) 2.3 2.5 v
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 63 data sheet 14. test conditions figure 14.1 test setup note diodes are in3064 or equivalent. 14.1 key to switching waveforms figure 14.2 input waveforms and measurement levels table 14.1 test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5ns input pulse levels 0.0 or v io v input timing measurement reference levels 0.5 v io v output timing measurement reference levels 0.5 v io v 2.7 k c l 6.2 k 3.3 v device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v output measurement level input 0.5 v io 0.5 v io
64 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 15. ac characteristics notes 1. not 100% tested. 2. see figure 14.1 on page 63 and table 14.1 on page 63 for test specifications. figure 15.1 v cc power-up diagram table 15.1 read-only operations parameter description test setup speed options unit jedec std. 90 110 t avav t rc read cycle time (note 1) min 90 110 ns t avqv t acc address to output delay ce#, oe# = v il max 90 110 ns t elqv t ce chip enable to output delay oe# = v il max 90 110 ns t pac c page access time v io = v cc = 3 v max 25 25 ns v io = 1.8 v, v cc = 3 v ? 30 t glqv t oe output enable to output delay v io = v cc = 3 v max 25 25 ns v io = 1.8 v, v cc = 3 v ? 30 t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns v cc re s et# t vc s ce# v cc min v ih t rh
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 65 data sheet figure 15.2 read operation timings figure 15.3 page read timings note * figure shows device in word mode. addresses are a1?a-1 for byte mode. t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df a23 - a2 ce# oe# a1 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
66 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet note not 100% tested. figure 15.4 reset timings notes 1. not 100% tested. 2. see the erase and programming performance on page 73 for more information. 3. for 1?16 words/1?32 bytes programmed. table 15.2 hardware reset (reset#) parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# input low to standby mode (see note) min 20 s t rb ry/by# output high to ce#, oe# pin low min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb t rh
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 67 data sheet notes 1. not 100% tested. 2. see the erase and programming performance on page 73 for more information. 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is written). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 15.5 on page 68 . table 15.3 erase and program operations parameter description speed options unit jedec std. 90 110 t avav t wc write cycle time (note 1) min 90 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) typ 240 s single word program operation (note 2) ty p 6 0 accelerated single word program operation (note 2) ty p 5 4 t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 90 110 ns
68 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet figure 15.5 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows de vice in word mode. figure 15.6 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out ry/by# t rb t busy t ch pa program command sequence (last two cycles) acc t vhh v hh v il or v ih v il or v ih t vhh acc t vhh v hh v il or v ih v il or v ih t vhh
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 69 data sheet figure 15.7 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 55 .) 2. illustration shows de vice in word mode. figure 15.8 data# polling timings (during embedded algorithms) note va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read c ycle. oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement tr u e addresses va t ch va va status data complement status data tr u e valid data valid data t poll t acc t ce t oeh t df t oh t rc
70 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet figure 15.9 toggle bit timings (during embedded algorithms) note va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cy cle, and array data read cycle. figure 15.10 dq2 vs. dq6 note dq2 toggles only when read at an address within an erase-suspended se ctor. the system may use oe# or ce# to toggle dq2 and dq6. oe# ce# we# addresses t oeh t dh t aht t aso t oeph t ce valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6 / dq2 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 71 data sheet notes 1. not 100% tested. 2. see the erase and programming performance on page 73 for more information. 3. for 1?16 words/1?32 bytes programmed. 4. if a program suspend command is issued within t poll , the device requires t poll before reading status data, once programming resumes (that is, the program resume command is written). if the suspend command was issued after t poll , status data is available immediately after programming resumes. see figure 15.11 on page 72 . table 15.4 alternate ce# controlled er ase and program operations parameter description speed options unit jedec std. 90 110 t avav t wc write cycle time (note 1) min 90 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) typ 240 s single word program operation (note 2) ty p 6 0 accelerated single word program operation (note 2) ty p 5 4 t whwh2 t whwh2 sector erase operation (note 2) ty p 0 . 5 s e c t rh reset# high time before write min 50 ns
72 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet figure 15.11 alternate ce# controlled write (erase/program) operation timings notes 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. illustration shows de vice in word mode. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling pbd for program 55 for erase t rh t whwh1 or 2 ry/by# t wh 29 for program buffer to flash 30 for sector erase 10 for chip erase pba for program 2aa for erase sa for program buffer to flash sa for sector erase 555 for chip erase t busy
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 73 data sheet 16. erase and programming performance notes 1. typical program and erase times assume the following conditions: 25 c, v cc = 3.0v, 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90 c; worst case v cc , 100,000 cycles. 3. programming time (typ) is 15 s (per word), 7.5 s (per byte). 4. accelerated programming time (typ) is 12.5 s (per word), 6.3 s (per byte). 5. write buffer programming time is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. in the pre-programming step of the embedded erase algo rithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to exec ute the command sequence(s) for the program command. see table 10.1 on page 51 and table 10.3 on page 53 for further information on command definitions. notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure (note 6) chip erase time s29gl032n 32 64 s29gl064n 64 128 total write buffer program time (notes 3 , 5 ) 240 s excludes system level overhead (note 7) total accelerated effective write buffer program time (notes 4 , 5 ) 200 chip program time s29gl032n 31.5 sec s29gl064n 63 table 16.1 tsop pin and bga package capacitance parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 10 pf bga tbd tbd pf c out output capacitance v out = 0 tsop 6 12 pf bga tbd tbd pf c in2 control pin capacitance v in = 0 tsop 6 10 pf bga tbd tbd pf c in3 #reset, #wp/acc pin capacitance v in = 0 tsop 27 30 pf bga tbd tbd pf
74 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 17. physical dimensions 17.1 ts048?48-pin standard thin small outline package (tsop) -x- x = a or b e/2 detail b c l 0.25mm (0.0098") bsc 0? detail a r gage line parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 c a-b s m 0.08mm (0.0031") section b-b e 0.10 c a2 plane seating c a1 see detail b s e e d e t a i l b b b b b see detail a s e e d e t a i l a 2 standard pin out (top view) 2 n +1 n n 1 4 2 a -a- -b- 5 9 e 5 d1 d 6 2 3 4 5 7 8 9 ts 048 mo-142 (b) ec 48 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 11.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 5? 0.20 18.50 12.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 3? 12.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for standard pin out (die up). not applicable. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. 3325 \ 16-038.10a
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 75 data sheet 17.2 ts056?56-pin standard thin small outline package (tsop) 6 2 3 4 5 7 8 9 ts 056 mo-142 (d) ec 56 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 13.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 8? 0.20 18.50 14.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 14.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for reverse pin out (die up). pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. n +1 2 n 1 2 n 3 reverse pin out (top view) c e a1 a2 2x (n/2 tips) 0.10 9 seating plane a see detail a b b ab e d1 d 2x 2x (n/2 tips) 0.25 2x 0.10 0.10 n 5 +1 n 2 4 5 1 n 2 2 standard pin out (top view) see detail b detail a (c) ? l 0.25mm (0.0098") bsc c r gauge plane parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 0.08mm (0.0031") m c a - b s section b-b detail b x e/2 x = a or b 3356 \ 16-038.10c
76 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 17.3 vbk048?ball fine-pitch ball grid array (bga) 8.15x 6.15 mm package 3338 \ 16-038.25 \ 10.05.04 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. side view top view seating plane a2 a (4x) 0.10 10 d e c 0.10 a1 c b a c 0.08 bottom view a1 corner b a m 0.15 c m 7 7 6 e se sd 6 5 4 3 2 a b c d e f g 1 h b e1 d1 c 0.08 pin a1 corner index mark package vbk 048 jedec n/a 8.15 mm x 6.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.35 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 77 data sheet 17.4 laa064?64-ball fortified ball grid array (bga) 13 x 11 mm package
78 s29gl-n mirrorbit ? flash family s29gl-n_01_09 november 16, 2007 data sheet 18. revision history section description revision 01 (february 12, 2007) initial release. revision 02 (february 26, 2007) global replaced lae064 package with laa064. page mode read corrected bit ranges in first paragraph. erase and programming performance modified maximum sector erase time in table. revision 03 (march 15, 2007) connection diagrams 64-ball fortified bga (laa 064) figure: changed inputs for balls f1 and f7. revision 04 (july 6, 2007) ordering information removed regulated v cc range and replaced 90 ns with 110 ns for low v io option added note 4 to package material set standard option sector addresses table corrected a table tsop pin and bga package capacitance added values for tsop revision 05 (august 10, 2007) ordering information removed leaded parts cfi table altered erase block region 1 & 2 revision 06 (september 18, 2007) global change document status to full production removed 70ns access speed command definitions (x16 mode) table corrected addresses for program operation command definitions (x8 mode) table corrected addresses for program operation revision 07 (october 22, 2007) global removed vid (12v) sector protect & unprotect features primary vendor-specific extended query table updated the data of cfi address 45hex revision 08 (november 2, 2007) primary vendor-specific extended query table updated the data of cfi address 2d hex thru 34 hex. s29gl064n (model 04) bottom boot sector addresses table updated s29gl064n (model 04) bottom boot sector addresses revision 09 (november 16, 2007) erase and program operations table changed t ds from 45 ns to 35 ns
november 16, 2007 s29gl-n_01_09 s29gl-n mirrorbit ? flash family 79 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2007 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries. other names used are for informational purp oses only and may be trademarks of their respective owners.

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